paradise.txt

比较详尽的VGA端口寄存器的文档

              3: One line repeated above character and two lines repeated
                 below the character
       4  Clear to unlock the Horizontal Display End Register (3d4h index 1)
       6  Clear to unlock the Vertical Display End Register (3d4h index 12h)
          and Overflow Register (3d4h index 7) bits 1 and 6

3C4h index 28h (R/W):  PR65 Reserved for future need                 (WD90c24)
bit  0-7  Reserved

3C4h index 29h (R/W):  PR66 Feature Register III                     (WD90c24)
bit  0-1  Reserved, must be set to 0
     2,6  TFT Dithering Mode Select. See 3C4h index 19h bits 3-4.
       3  If set VSYNC and HSYNC are forced to in-active low.
       4  If set PCLK is forced to inative low. In CRT-only mode BLANK and
          VID[0-7] are also forced to inactive low
       5  If set LP is the same as HSYNC and FP is the same as VSYNC
       7  If set enables Auxiliary Video Extender (AVE) Mode where the
          internal RAMDAC is driven from an external source

3C4h index 31h (R/W):  PR68 Programmable Clock Selection Register    (WD90c24)
bit  0-2  Display Memory Clock Select. In MHz:
            0: 55.035    1: 33.111    2: 59.957    3: 37.585
            4: 39.822    5: 44.297    6: 47.429    7: 49.219
     3-4  Video Dot Clock Select bits 2-3. Bits 0-1 are in 3C2h/3CCh bits 2-3.
          The value 2 selects programmed clock via index 32h. In MHz:
            0: 29,979    1: 77,408    2: Prog      3: 80,092
            4: 25,175    5: 28,322    6: 65,000    7: 36,000
            8: 39,822    9: 50,114   10: 42,060   11: 44,297
           12: 31,500   13: 35,501   14: 75,166   15: 50,114

3C4h index 32h (R/W):  PR69 Programmable VCLK Frequency Register     (WD90c24)
bit  0-7  If Video Dot Clock 2 is selected, the Video Dot Clock is calculated
          as:  (This register) * 0.447443 MHz.  Min 25.017MHz, Max 85.014MHz

3C4h index 33h (R/W):  PR70 Mixed Voltage Override Register          (WD90c24)
bit    0  If set selects 3.3V for AVDD, if clear 5V
       1  If set selects 3.3V for MVDD, if clear 5V
       2  If set selects 3.3V for FPVDD, if clear 5V
       3  If set selects 3.3V for BVDD, if clear 5V
       4  If set selects 3.3V for PVDD, if clear 5V
       5  If set bits 0-4 determines the Voltage used

3C4h index 34h (R/W):  PR71 Programmable Refresh Timing Register     (WD90c24)
bit  0-7  If 3C4h index 19h bit 1 is set the CKIN clock (typically 32kHz) is
          divided by:  ((this register) +1 ) *8

3C4h index 35h (R/W):  PR72 Programmable Clock                       (WD90c24)
bit  4-6  Write 5 to unlock 3C4h index 31h, any other value locks it

3C4h index 36h (R/W):  PR73 VGA Status Detect                        (WD90c24)
bit    0  If set the Core Voltage is 3.3V, if clear 5V
       4  If set the FPUSR0 signal is active low, if clear active high
     5-6  I/O and Memory Detect. 1: I/O Detection, 2: Memory Detection,
           3: I/O & Memory Detection
       7  If set enables Status Detect

Note: The WD90c33 appears to use 3C4h index C0h-FFh

3CEh index  9  (R/W):  PR0A Address Offset A
bit  0-6  (<WD90c24) Added to bit 12-18 of video memory address if
            Bank A selected. (Reads if 3C4h index 11h bit 7 set, A800h-AFFFh
            if 3CEh index Bh bit set and 64k config B000h-BFFFh if 128k
            config. A000h-AFFFh else).
     0-7  (WD90C24,26,3x) same but bit 12-19 rather than 12-18.

3CEh index 0Ah (R/W): PR0B Address Offset B
bit  0-6  (<WD90c24) Added to bit 12-18 of video memory address if
            Bank B selected. (Writes if 3C4h index 11h bit 7 set, A000h-A7FFh
            if 3CEh index 0Bh bit 3 set and 64k config, A000h-AFFFh if 128k
            config).
     0-7  (WD90C24,26,3x) Same but bit 12-19 rather than 12-18.

3CEh index 0Bh (R/W):  PR1 Memory Size
bit    0  Enable on card ROM if set. Latched on Poweron
       1  Select 16 bit ROM access if set. Latched on Poweron
       2  Select 16 bit Memory access if set
       3  PR0B enabled if set, else use PR0A for both banks
     4-5  Memory Map.  0: A000h-BFFFh standard VGA,
            1: 1st 256K of a 1MB area, 2: 1st 512K of a 1MB area, 3: 1MB area
          For linear mapping 3C4h index 14h (and for Local Bus systems 2DF2h)
          select the location of the 1MB buffer in system memory
     6-7  Installed memory:
            0  256k VGA standard
            1  256k PVGA bank switching
            2  512k PVGA bank switching
            3    1M PVGA bank switching

3CEh index 0Ch (R/W):  PR2 Video Configuration
bit    0  Force VCLK (overrides SEQ1 bit 3).
       1  Third Clock Select Line VCLK2
          This bit appears to be inverted on the WD90c1x and WD90c2x, compared
          to the WD90c00 and PVGA1
     2,5  Character Map Select/Underline
            0  Characters are taken from plane 2
            1  do, but characters are underlined if bit 0 of the characters
               attribute is set.
            2  Characters are taken from plane 3.
            3  If bit 3 of the characters attribute is set the character is
               taken from plane 3, else from plane 2.
     3,4  Character Clock Period Control
            0  IBM VGA character Clock (8 or 9 dots wide).
            1  7 dots (used for 132 character modes).
            2  9 dots
            3  10 dots
          Selecting 10 dots/character modifies the horizontal PEL panning
          register (3C0h index 13h).
       6  6845 Compatibility Mode (6845 if set, EGA/VGA if clear).
       7  AT&T/M24 Mode Enable, 400 line enable if set

3CEh index 0Dh (R/W):  PR3 CRTC Control
bit    0  Lock Vertical Timing (3d4h index 6,(7 bit 0,2,3,5,7),9 bit 5,
            (3Dh bit 0,2,3),10h,11h bits 0-3,15h,16h) if set
       1  Lock Prevention. Prevent locking through the Vertical Retrace
          register (3d4h index 11h bit 7).
       2  Multiply Cursor Start, Cursor Stop, Preset Row Scan and Maximum Scan
          Line registers by 2
     3-4  CRTC Display Start Address bits 16-17. Bits 0-15 are in 3d4h index
          0Ch,0Dh. Also bits 16-17 of the Cursor Address (3d4h index 0Eh/0Fh).
       5  Lock Horizontal Timing Registers (3d4h index 0-5,17h bit 2) if set
       6  Lock HSYNC Polarity (3C2h/3CCh bit 7) if set
       7  Lock VSYNC Polarity (3C2h/3CCh bit 6) if set
Note: 3d4h index 0-7 are locked if either 3d4h index 11h bit 7 or bits 0 or 5
      of this register is set.

3CEh index 0Eh (R/W): PR4 Video Control
bit    0  Extended 256 color Shift register Control. Configures the video
          shift registers for extended 256 color mode if set
       1  EGA compatibility. Disables reads of all registers that are
          writeonly on the EGA, and of PR0-5 if set.
       2  Lock internal Palette and Overscan registers if set
       3  Override CGA Enable Video bit. Overrides the CGA "enable video"
          bit 3 of 3D8h if set
       4  Tri-state Memory Control Outputs if set
       5  Tri-state Video (VID0-7) outputs. On the WD90c00 and later also
          tri-states the HSYNC, VSYNC and BLNKN
       6  (PVGA1A) Tristate HSYNC, VSYNC, BLNKN
          (WD90c00 +) Select PCLK=VCLK if set, PCLK = 1/2 VCLK if clear
       7  BLNK/Display Enable. If set the BLNKN output supplies PRE-Display
          Enable (1 pixel) rather than the BLNKN signal

3CEh index 0Fh (R/W): PR5 General Purpose Status and PR Register
bit  0-2  Extended registers PR0-4 Unlocked if set to 5
       3  (R) CNF bit 8. Set for TTL (EGA compatible) display, clear for
           Analog (VGA compatible) display.
       4  (W) Read protect PR0-4 if set
          (R) CNF bit 4
       5  (R) CNF bit 5
       6  (R) CNF bit 6
       7  (R) Multisync if set, fixed frequency else (CNF bit 7 = Switch 1).

3d4h index 29h (R/W): PR10 Unlock PR11-17 Registers               (not PVGA1A)
bit  0-2  Write of PR11-18 enabled if set to 5, disabled for all other values
     3,7  Read of PR11-18 enabled if bit 3 clear and bit 7 set, any other
          value causes reads of PR11-18 to return FFh

3d4h index 2Ah (R/W): PR11 EGA Switches                           (not PVGA1A)
bit    0  Lock 8/9 Dot Character Clock. Inhibits writes to 3C4h index 1 bit 0
          if set.
       1  Lock Graphics and Sequencer Screen Control if set
          Inhibits write to 3CEh index 5 bit 5-6, 3C4h index 1 bit 2-5 and
          3C4h index 3 bit 0-5.
       2  Lock Clock Select
       3  EGA Emulation on Analog Display
     4-7  EGA Switch 1-4. Latched from MD12-15 on reset
       4  (WD90c24) CNF17. Together with CNF2 determines bus type:
     5-7  (WD90c24) Memory Mode. 4: 2 256Kx16, 5: 1 256Kx16

3d4h index 2Bh (R/W): PR12 Scratch Pad Register                   (not PVGA1A)
bit  0-7  Reserved

3d4h index 2Ch (R/W): PR13 Interlace H/2 Start                    (not PVGA1A)
bit  0-7  Interlace H/2 Start. Adjusts Horizontal Sync for interlace.
          This register should be programmed with:
            (3d4h index 4) - (3d4h index 0 +5)/2 + (3d4h index 5 bits 5-6)

3d4h index 2Dh (R/W): PR14 Interlace H/2 End                      (not PVGA1A)
bit  0-4  Interlace H/2 End. Adjusts horizontal Sync width. Should be
          programmed with the low 5 bits of: (index 2Ch) + (?)
       5  Interlace enable if set
       6  Vertical Double Scan for EGA on PS/2 Display if set
       7  Enable Vertical retrace interrupts if set

3d4h index 2Eh (R/W): PR15 Miscellaneous Control #1               (not PVGA1A)
bit    0  Disable borders if set
       1  Select Display Enable Timing. If set BLNKN supplies Display Enable,
          if clear BLNKN supplies Pre-Display Enable (one dot-clock prior to
          active video). This bit is only active if 3CEh index 0Eh bit 7 is
          set
       2  Enables page mode addressing in alpha modes if set. Speeds up the
          display (I.e. reduces the memory bandwidth used) by utilising the
          Fast Page Mode found on all newer DRAM chips. This should be done
          for 132 character text modes.
       3  Interlace compatible with 8514/A timing if set (should only be set
          in interlaced modes). Causes Vertical Sync to be generated from the
          trailing edge of non-skewed Horizontal Sync, rather than the leading
          edge. Also removes 2 VCLK delays from the default VGA video path.
       4  VCLK=MCLK. If set MCLK is used for all video timings.
       5  VCLK1,VLKC2 Latched Outputs. If set bits 2 & 3 of 3C2h/3CCh are
          output on VCLK1,VCLK2
       6  High VCLK. Set if VCLK is much faster than MCLK (more then 50%
          faster). Should also be set in all 256color extended modes
       7  Enable read of 46E8h if set

3d4h index 2Fh (R/W): PR16 Miscellaneous Control #2               (not PVGA1A)
bit    0  If set prevents writes of the DAC registers (3C6h-3C9h).
       1  Standard VGA memory if set (Forces 256K configuration)
       2  Enable Page Bit for Odd/Even.
     3-4  Bit 16,17 of CRTC Address Counter Offset.
     5-6  CRTC Address Counter Width
           0= 256k, 1=128K, 2,3=64K
       7  If set locks external 46E8h register

3d4h index 30h (R/W): PR17 Miscellaneous Control #3               (not PVGA1A)
bit    0  Maps out ROM at C600h-C67Fh if set
       1  (not WD90C00) If set locks the Hercules Compatibility register
           (3BFh)
       2  (not WD90C00) Enables 64k ROM at C000h-CFFFh if set
       3  (not WD90C00) Maps out ROM at C600h-C6FFh if set
       4  (not WD90C00) If set PCLK = VCLK/2
       5  (not WD90C00) If 3CEh index 0Ch bit 3-4 = 3, this bit selects 6 dot
           font if clear, 10dot font if set

3d4h index 31h-37h (R):                                         (WD90C11,24 +)
Contains the text "WD90Cxx" (57h 44h 39h 30h 43h), where xx is model dependent
           36h:  37h:  Text:        Chip:
           31h   31h   'WD90C11'    WD90C11
           32h   34h   'WD90C24'    WD90C24
           32h   36h   'WD90C26'    WD90C26
           33h   30h   'WD90C30'    WD90C30
           33h   31h   'WD90C31'    WD90C31
           33h   33h   'WD90C33'    WD90C33
Note: for the WD90c24 (and probably the 26) these registers are only visible
      when the Flat Panel extensions and Mapping Registers are disabled.
      (Write 00h to 3d4h index 34h and 35h).
Note: 3d4h index 38h-3Dh appears to hold other chip information like revision
      level, however the format is not known yet.
Note: These registers have apparently never been documented by Western Digital

3d4h index 31h (R/W):  PR18 Flat Panel Status Register          (WD90c2x only)
bit  0-1  LCD Panel Select. 0: Dual Panel LCD, 1: Plasma/EL, 3: Single Panel
          LCD Display
       2  (W) If set enables TFT Color Interface
       4  Together with 3d4h index 3Eh bit 3 selects the Reverse Video mode
          for Flat Panel output:
             31h bit 4    3Eh bit 3    Effect:
                 0            0        Normal text and graphics
                 1            0        Reversed text and graphics
                 1            1        Reversed text, normal graphics
       5  If set selects 256K color palette STN dithering, if clear selects 4K
          palette dithering
       6  If set enables free running clock for EL, Plasma or TFT panel
       7  If set an external RAMDAC is selected and the internal RAMDAC is
          disabled, if clear the internal RAMDAC is used.

3d4h index 32h (R/W):  PR19 Flat Panel Control 1                (WD90C2x Only)