paradise.txt

比较详尽的VGA端口寄存器的文档

  Paradise/Western Digital Super VGA Chips.

               Max mem   Max 16col  256 col
    PVGA1A     512k/1M     800x600   640x480
    WD90C00    512k/1M    1024x768   800x600   also known as PVGA1B
    WD90C10    256k        640x480   320x200
    WD90C11    512k       1024x768   800x600
    WD90C20                800x600   640x480?  LCD/plasma controller derived
                                               from WD90C00.  32 grey scales
    WD90C22                                    As C20, but 64 grey scales
    WD90c24    208pin   Max 1M RAM, 1280x1024 16c, 1024x768 256c.
               Builtin 15/16bit DAC. LCD controller with BitBLT, line draw and
               VESA local bus interface. Supports 3.3V or 5V operation
    WD90c24A
    WD90c26A                                   LCD controller. Can drive LCD
                                               and CRT simultaneously. 3.3V
    WD90C30    1M         1024x768  1024x768   (D-step)
    WD90C31    1M        1280x1024  1024x768   (1DW - accelerator) Hardware
                                               Cursor, BitBLT.
    WD90C33    2M                  1280x1024   Accelerator. as WD90c31, but
                                               with 8-level instruction FIFO.
                                               VESA local bus interface.
    WD90C35              Next version?

Support chips:
    WD90c55                                 Color LCD interface for WD90c20/22
    WD90c56                                 Local Bus Interface for WD90c31


 94h (W): Setup Register     (Micro Channel)

102h (R/W): VGA Sleep Register    (setup mode only)
bit    0  VGA enabled if set.
     1-7  Reserved.
Note: this register can only be accessed in setup mode.

3B8h (W):  Hercules/MDA Mode Control Register
bit    0  High Resolution (80x25) mode enabled if set
       1  If set allows access to 3BFh, if clear disables access to 3BFh and
          thus forces alpha mode.
       3  If set video is active
       5  If set blinking is enabled
       7  (Hercules mode) If bit 1 is set and 3BFh bit 0 is set, this bit
          selects the page to display. 0: B000h:0, 1: B800h:0
Note: This register is only available in MDA/Hercules compatibility modes

3BAh (R):  CRT Status Register MDA Operation
bit    0  If set either blanking or border is active
       3  If set B/W Video is enabled
       7  If clear Vertical Retrace is active

3BFh (W):  Hercules Mode Register
bit    0  Set in graphics modes, clear in alpha modes
       1  If set the upper 32K at B800h:0 is accessible
Note: This register is only available in Hercules compatibility modes

3C3h (W): Global Enable Register
bit    0  VGA Motherboard Enable if set
Note: this register is used for MicroChannel and motherboard systems, 46E8h
      for all other systems.

3C4h index  3  (R/W): Reconfigured Character Map Select
bit  0-2  Offset of character map in plane 2/3 in 8k blocks
     3-4  Character map select from plane:
            0: plane 2
            1: plane 2 if attr. bit 3 set, plane 3 else
            2: plane 3 if attr. bit 3 set, plane 2 else
            3: plane 3

3C4h index  6  (R/W):  PR20 Unlock Paradise Extended Registers (WD90c10+ only)
bit  0-7  Write 48h to this register to unlock the Paradise Extended Sequencer
          Registers (3C4h index >7)

3C4h index  7  (R/W):  PR21 Display Configuration Status       (WD90C10+ Only)
bit    0  (R) Monitor type. TTL if set, Analog if clear. This is the same as
              3CEh index 0Fh bit 7
       1  (R) EGA emulation if set, VGA if clear. This is the same as 3CEh
              index 0Eh bit 1.
       2  (R) 6845 compatibility if set. This is the same as 3CEh index 0Ch
              bit 6.
       3  (R) Color mode if set, mono if clear. This is the same as 3CCh bit 0
     4-7  Scratch Pad (Display Configuration)

3C4h index 08h (R/W):  PR22 Scratch Pad Register               (WD90c10+ only)
bit  0-7  Scratch Pad

3C4h index 09h (R/W):  PR23 Scratch Pad Register               (WD90c10+ only)
bit  0-7  Scratch Pad

3C4h index 10h (R/W):  PR30A Write Buffer and FIFO Control     (WD90c11+ only)
bit  0-1  (WD90c24,26,31+?) Display FIFO control. Determines when the FIFO
            will request a memory cycle: 0: one level empty, 1: two, 2: three,
             3. four
     2-3  (WD90c24,26,31+?) FIFO depth. 0: 8 levels, 1: 4 levels,
             2,3: 2 levels
       4  If set disables 16bit unchained mode (for test only)
       5  If set the Display Memory path is 16bit, if clear 32bit
     6-7  (WD90c24,26,31+?) Write Buffer Control. 0: Write Buffer is one level
            deep, 1: two, 2: three, 3: four

3C4h index 11h (R/W):  PR31 System Control Interface           (WD90C1x+ Only)
bit    0  16 bit access to CRTC, Graphics Controller and Sequencer Registers
          if set
       1  16 bit access to Attribute Registers if set and bit 0 set.
          If so 3C0h is index and 3C1h is data port.
       2  Enable Write buffer if set. Reduces number of wait states for writes
          to display memory
     3-4  Read Rdy Cntrl. Enhanced speed depending on host bus speed:
           0:  RDY is inserted at the end of a CPU memory cycle. Used for
               Local Bus. Power on default (WD90c24)
           1:  RDY is inserted 1 MCLK cycle before the end of a CPU memory
               cycle. Use for 10MHz or slower ISA systems
           2:  RDY is inserted 2 MCLK cycles before the end of a CPU memory
               cycle.
           3:  RDY is inserted 1 MCLK cycle after the end of a CPU memory
               cycle. Use for 12MHz ISA systems
       5  Enhanced text mode operations if set
       6  Enhanced operation on blank lines if set. Prevents screen refresh
          memory cycles during Vertical Blanking
       7  (WD90C1x,24+ Only) RW Offset. If set Bank reg PR0A is used for
           read cycles and PR0B for write cycles, else PR0B is used for
           A000h-A7FFh and PR0A for A800h-AFFFh.

3C4h index 12h (R/W): PR32 Miscellaneous Control #4            (WD90C1x+ Only)
bit    0  If set use special CPU mapping for 132column text modes ?
       1  If set allows reading the registers that are write-only in
          compatibility modes (EGA,CGA,MDA registers)
       2  (WD90c1x,3x) Clock Select bit 3. Bit 2 is in 3CEh index 0Ch bit 1,
            bits 0-1 are in 3C2h/3CCh bits 2-3.
     2-3  (WD90c24) Controls the FPUSR0 output pin. 0: set low, 1: set high,
            2,3: pin is controlled by 3C4h index 15h bits 0-2
     4-5  Controls the FPUSR1 output pin. 0: set low, 1: set high, 2,3: pin is
          controlled by 3C4h index 15h bits 3-5
       6  Disable Cursor Blinking if set
       7  (not WD90c24) Enable External Sync

3C4h index 13h (R/W):  PR33A DRAM Timing and Zero Wait State Control
                                                               (WD90c1x+ only)
bit  0-1  Length of RAS precharge. 0: 2.5MCLK cycles +d, 1: 3MCLK, 2: 2MCLK,
           3: 2.5MCLK
       2  If set the CAS cycle starts 1.5 MCLK cycles after RAS low, if clear
           2.5 MCLK cycles after RAS low
     3-4  CAS timing.
               CAS cycle width    CAS low      CAS high
           0:   2 MCLK cycles    1MCLK +  d    1MCLK -  d
           1:   2 MCLK cycles    1MCLK + 2d    1MCLK - 2d
           2:   2 MCLK cycles    1.5 MCLK      0.5 MCLK
     6-7  Zero Wait State Control. Controls the output on the ZWST pin
           0:  Reserved, do NOT use
           1:  Low if the internal write buffer is ready AND the memory
               address is decoded.
           2:  As 1, but also require that MWR is 0
           3:  As 2, but also low if an I/O write to the VGA occurs.
Note: the time d is 3-7ns for 5V operation, 5-10ns for 3.3V

3C4h index 14h (R/W):  PR34A Display Memory Mapping Register   (WD90C1x+ only)
bit  0-3  Bits 20-23 of the memory address where the 1MB video buffer is
          located if using linear address buffer. For Local Bus versions also
          see 2DF2h for the upper 8 address bits.
     4-5  Set to enable Linear Frame buffer ???
       6  (WD90c33) Bit 8 of PR0A. Bits 0-7 are in 3CEh index 9.

3C4h index 15h (R/W):  PR35A FPUSR0,FPUSR1 Output Select       (WD90c1x+ only)
bit  0-2  Controls the output on the FPUSR0 pin if 3C4h index 12h bit 3 is set
           0:  High if an I/O address is decoded
           1:  High if fetching character attribute from DRAM
           2:  Low if the internal write buffer is not empty
           3:  High if a CPU read cycle is occurring
           4:  Low if a write buffer cycle is occurring
     3-5  Controls the output on the FPUSR1 pin if 3C4h index 12h bit 5 is set
           0:  High if fetching font from DRAM
           1:  High if fetching graphics data from DRAM
           2:  High if the internal write buffer is ready
           3:  High if a CPU write cycle is occurring
           4:  Low if a CPU write cycle is not caused by the write buffer

3C4h index 16h (R/W):  PR45 Video Signature Analyser Control      (WD90c24,26)
bit    0  Set to start generation of a signature for a frame. Must be reset
          and then set again for the next signature.
       1  Clearing this bit initialises the Signature Analyser by preloading
          the value 0001h. Must be set before a signature can be generated.
       2  If set an all-zero pattern is used as input to the Signature
          Analyser rather than the output of the RAMDAC
       3  Set to enable access to the Signature Analyser Data registers
          (3C4h index 17h,18h)

3C4h index 17h W(R/W):  PR45A,B Signature Analyser Data           (WD90c24,26)
bit 0-15  Result from Signature Analyser

3C4h index 19h (R/W):  PR57 Feature Register I                    (WD90c24,26)
bit    0  Bank B Enable. If set memory accesses and refresh operations to bank
          B display memory is enabled, if clear disabled.
       1  Source for REFRESH timing. If set CKIN divided by 3C4h index 34h, if
          clear the REFRESH input pin.
       2  Panel Power Control. If 3d4h index 32h bit 4 is set this bit
          controls the PNLOFF output. 0: PNLOFF high, 1: PNLOFF low
     3-4  TFT Dithering Mode Select. Together with 3C4h index 29h bits 2,6 and
           3C4h index 21h bit 4 this controls the dithering algorithm.
          Index 21h  29h  19h
          Bit    4   2 6  3-4
                                 9bit TFT modes:
                 0   0 0   0     2-Frame Dithering, 27K colors
                 0   0 0   2     No Dithering, 512 colors
                 0   0 0   3     Space Dithering, 27K colors
                 0   1 0   0     2-Frame Dithering, 180K colors
                 0   1 0   1     2 and 3 Frame Dithering, 256K colors
                 0   1 0   2     No Dithering, 512 colors
                                 12bit TFT modes:
                 0   x 1   0     2-Frame Dithering, 226K colors
                 0   x 1   1     2-Frame Dithering, 226K colors
                 0   x 1   2     No Dithering, 4K colors
                 0   x 1   3     Space Dithering, 226K colors
                                 18bit TFT modes:
                 1   x x   2     No Dithering, 256K colors
          All other combinations are invalid
       5  If set enables self-refresh when entering Powerdown mode
       6  Refresh Clock (REFLCL) Input. Only used in Local Bus mode.
          If clear the REFLCL pin provides the refresh clock source (typically
          32KHz). This overrides bit 1.

3C4h index 20h (R/W):  PR58 Feature Register II                   (WD90c24,26)
bit    0  Scratch Pad

3C4h index 21h (R/W):  PR59 Memory Arbitration Cycle Setup        (WD90c24,26)
bit  0-2  Arbitration Cycle Select. Sets the length of the Arbitration Cycle
          in units of 160ns (for 25MHz VCLK = 4 VCLK cycles).
       3  If set enables Space Dithering in Mode 13h.
       4  If set selects 18bit TFT, if clear 9 or 12bit TFT
       5  If set the ENDATA output is low, if clear high

3C4h index 24h (R/W):  PR62 FR Timing Register                    (WD90c24,26)
bit  0-7  This value controls the period of the Frame Rate (FR) signal.
          Program with 1/4th the number of lines in the FR period.

3C4h index 25h (R/W):  PR63 Read/Write FIFO Control                  (WD90c24)
bit    0  If set enables write operations to the Frame Buffer
       1  If set enables read operations from the Frame Buffer
     2-7  The time the Frame Buffer can be accessed in MCLKs ?

3C4h index 26h (R/W):  PR58A Memory Map Register for BLT Access
                             in PI/Local Bus                         (WD90c24)
bit  0-1  Enables Memory Mapping to I/O ports.
           0: No I/O Memory Mapping.
           1: Map I/O ports 23C0h-23C5h. Writes to A0000h-AFFFFh are decoded
               to one of the registers 23C0h-23C7h from the low 3 address bits
           3: Map I/O port 23C4h only. Writes to A0000h-AFFFFh are decoded to
              register 23C4h
     2-3  Select True Color Mode. 0: Normal Palette, 1: 5-6-5 64K True color,
           2: 6-5-5 64K True Color, 3: 5-5-5 32K True Color
       4  If set data is shifted out of the video FIFO in 16bit chunks.

3C4h index 27h (R/W):  PR64 CRT Lock Control II                      (WD90c24)
bit  0-1  Vertical Expansion Selected (only in 400 line modes):
            0,2: No enhanced expansion
              1: 3 lines repeated below character