📄 mpgiface.h
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#define DENC_CFG5_BKR 0x08 /* blanking of DAC R */
#define DENC_CFG5_BKG 0x04 /* blanking of DAC G */
#define DENC_CFG5_BKB 0x02 /* blanking of DAC B */
#define DENC_CFG5_DACINV 0x01 /* DAC inverted */
/* ---- CFG6 */
#define DENC_CFG6_SOFTRESET 0x80 /* Soft reset */
#define DENC_CFG6_JUMP 0x40 /* Line skip/insert */
#define DENC_CFG6_DECINC 0x20 /* " */
#define DENC_CFG6_FREEJUMP 0x10 /* " */
#define DENC_CFG6_CHGI2C 0x02 /* chip address */
#define DENC_CFG6_MAXDYN 0x01 /* Max dynamic magnitude */
/* ----- STATUS */
#define DENC_STS_HOK 0x80 /* Hamming decoding of ODD/EVEN signal from YCRCB */
#define DENC_STS_ATFR 0x40 /* Frame synchronisation flag */
#define DENC_STS_BUF2_FR 0x20 /* Close caption access status */
#define DENC_STS_BUF1_FR 0x10 /* Close caption access status */
#define DENC_STS_FLD2 0x08 /* Field number */
#define DENC_STS_FLD1 0x04 /* Field number */
#define DENC_STS_FLD0 0x02 /* Field number */
#define DENC_STS_JUMPING 0x01 /* Delay overflow */
#endif
/*
* AUDIO register map for STi5500
*/
/*
AUD_ABG, AUD_ABL, AUD_ABS, AUD_ABT doest'nt exist in the audio register area : see video area
*/
#define AUD_ADA (AUDIO_REGISTERS_BASE + 0x6C) /* 6 bit reg */
#define AUD_ANC (AUDIO_REGISTERS_BASE + 0x06)
#define AUD_BBE (AUDIO_REGISTERS_BASE + 0x70) /* 1 bit reg */
#define AUD_CDI (AUDIO_REGISTERS_BASE + 0x18)
#define AUD_CRC (AUDIO_REGISTERS_BASE + 0x2A) /* 2 bit reg */
#define AUD_DEM (AUDIO_REGISTERS_BASE + 0x46) /* 2 bit reg */
#define AUD_DIF (AUDIO_REGISTERS_BASE + 0x6F)
#define AUD_DIV (AUDIO_REGISTERS_BASE + 0x6E) /* 6 bit reg */
#define AUD_ESC (AUDIO_REGISTERS_BASE + 0x0A) /* 34 bit reg */
#define AUD_ESC_EXT (AUDIO_REGISTERS_BASE + 0x0F) /* 34 bit reg */
#define AUD_EXT (AUDIO_REGISTERS_BASE + 0x1F) /* 2 bit reg */
#define AUD_FFL (AUDIO_REGISTERS_BASE + 0x14) /* 16 BIT REG */
#define AUD_FOR (AUDIO_REGISTERS_BASE + 0x19)
#define AUD_HEADER (AUDIO_REGISTERS_BASE + 0x5E)
#define AUD_HDR_LW_LB (AUDIO_REGISTERS_BASE + 0x5E) /* LoByte of LoWord AUD_HDR [7:0] */
#define AUD_HDR_LW_HB (AUDIO_REGISTERS_BASE + 0x5F) /* HiByte of LoWord AUD_HDR [15:8] */
#define AUD_HDR_HW_LB (AUDIO_REGISTERS_BASE + 0x60) /* LoByte of HiWord AUD_HDR [23:16] */
#define AUD_HDR_HW_HB (AUDIO_REGISTERS_BASE + 0x61) /* HiByte of HiWord AUD_HDR [31:24] */
#define AUD_IDE (AUDIO_REGISTERS_BASE + 0x24)
#define AUD_IFT (AUDIO_REGISTERS_BASE + 0x52)
#define AUD_ITS (AUDIO_REGISTERS_BASE + 0x5B)
#define AUD_IMS (AUDIO_REGISTERS_BASE + 0x5C) /* AUD_IMS [1:0] */
#define AUD_ISS (AUDIO_REGISTERS_BASE + 0x36) /* 3 bit reg */
#define AUD_ITM (AUDIO_REGISTERS_BASE + 0x1C) /* 15 bit reg */
#define AUD_ITR (AUDIO_REGISTERS_BASE + 0x1A) /* 15 bit reg */
#define AUD_LCA (AUDIO_REGISTERS_BASE + 0x20) /* 6 bit reg */
#define AUD_LCK (AUDIO_REGISTERS_BASE + 0x28) /* 2 bit reg */
#define AUD_LRP (AUDIO_REGISTERS_BASE + 0x11)
#define AUD_LAT (AUDIO_REGISTERS_BASE + 0x3C)
#define AUD_MUT (AUDIO_REGISTERS_BASE + 0x30)
#define AUD_ORD (AUDIO_REGISTERS_BASE + 0x38)
#define AUD_P18 (AUDIO_REGISTERS_BASE + 0x16)
#define AUD_PLY (AUDIO_REGISTERS_BASE + 0x2E)
#define AUD_PTS (AUDIO_REGISTERS_BASE + 0x62)
#define AUD_PTS_4 (AUDIO_REGISTERS_BASE + 0x66)
#define AUD_RCA (AUDIO_REGISTERS_BASE + 0x1E) /* 6 bit reg */
#define AUD_RES (AUDIO_REGISTERS_BASE + 0x40)
#define AUD_REV (AUDIO_REGISTERS_BASE + 0x6D) /* 8 bit reg */
#define AUD_RST (AUDIO_REGISTERS_BASE + 0x42)
#define AUD_SCM (AUDIO_REGISTERS_BASE + 0x25)
#define AUD_SCP (AUDIO_REGISTERS_BASE + 0x53)
#define AUD_SEM (AUDIO_REGISTERS_BASE + 0x2C) /* 2 bit reg */
#define AUD_SFR (AUDIO_REGISTERS_BASE + 0x44) /* 2 bit reg */
#define AUD_SID (AUDIO_REGISTERS_BASE + 0x22) /* 5 bit reg */
#define AUD_SKP (AUDIO_REGISTERS_BASE + 0x32)
#define AUD_SYE (AUDIO_REGISTERS_BASE + 0x27)
#define AUD_SYN (AUDIO_REGISTERS_BASE + 0x23) /* 2 bit reg */
#define AUD_SYS (AUDIO_REGISTERS_BASE + 0x26) /* 2 bit reg */
/*
* AUD_ITM/ AUD_ITR 15 bit reg
*/
#define AUDIO_INT_NEW_FRAME 0x4000
#define AUDIO_INT_FIFO_FULL 0x2000
#define AUDIO_INT_FIFO_AT_THRESHHOLD 0x1000
#define AUDIO_INT_DEEMPHASIS_CHANGED 0x0400
#define AUDIO_INT_SAMPLING_FREQUENCY_CHANGED 0x0200
#define AUDIO_INT_PCM_OUTPUT_UNDERFLOW 0x0100
#define AUDIO_INT_ANC_REGISTER_FULL 0x0080
#define AUDIO_INT_CRC_ERROR_DETECTED 0x0020
#define AUDIO_INT_PTS_REGISTERED 0x0004
#define AUDIO_INT_HEADER_REGISTERED 0x0002
#define AUDIO_INT_CHANGE_IN_SYNC_STATUS 0x0001
/* Exported Variables ------------------------------------------------------- */
/* Exported Macros ---------------------------------------------------------- */
/* -------------------------------------
Now the access function prototypes,
and the access macro's for registers
NOTE due to timing sensitivity I
have split the large accesses
for audio into separate 8
bit accesses.
------------------------------------- */
/* ============================================================================= */
/* GENERIC MACRO */
/* ============================================================================= */
#define MPEG_WRITE_VIDEO_COMPRESSED_PACKET( pkt, pktlen ) __asm{ldabc pktlen, MPEG_VIDEO_DMA, pkt; out; }
#define MPEG_WRITE_AUDIO_COMPRESSED_PACKET( pkt, pktlen ) __asm{ldabc pktlen, MPEG_AUDIO_DMA, pkt; out; }
#define DEVICE_WRITE( address, value ) __asm{ ld value; ld address; devsw; }
#define DELAY(n) \
__asm \
{ \
ajw -2; \
ldc n; \
bcnt; \
stl 1; \
ldc 0; \
stl 0; \
/* loop: */ \
ldc 0; ldc 0; ldc 0; ldc 0; ldc 0; \
ldlp 0; \
ldc 10; \
lend; \
ajw 2; \
}
/*
* note that the mpeg write/read macros receive value on 32 bits
* but deal only with the 8 lsb for the mpeg register
*/
/*#define USE_OS20*/
#ifdef USE_OS20
#define MPEG_WRITE_REGISTER( address, value ) \
{ \
volatile unsigned char *mpeg_reg_pointer ; \
interrupt_lock(); \
mpeg_reg_pointer = (volatile unsigned char*)address; \
*mpeg_reg_pointer = (volatile unsigned char)(value & 0xff); \
interrupt_unlock(); \
}
#define MPEG_READ_REGISTER( address, value ) \
{ \
volatile unsigned char *mpeg_reg_pointer ; \
interrupt_lock(); \
mpeg_reg_pointer = (volatile unsigned char*)address; \
value &= ~0xff; \
value |= (unsigned int)(*mpeg_reg_pointer); \
interrupt_unlock(); \
}
#else
#define MPEG_WRITE_REGISTER( address, value ) \
__asm{ \
ldc 0xff; gintdis; \
ld value; \
ldc address; \
sb; \
ldc 0xff; gintenb; \
}
#define MPEG_READ_REGISTER( address, value ) \
__asm{ \
ldc 0xff; gintdis; \
ldc address; \
lb; \
ld &value; \
sb; \
ldc 0xff; gintenb; \
}
#endif
/* ============================================================================= */
/* AUDIO REGISTER MACRO */
/* ============================================================================= */
#define MPEG_WRITE_AUDIO8( address, value ) \
{ \
MPEG_WRITE_REGISTER( address, value ); \
}
/* --- NOTE 16 bit quantities in the audio block are little endian and on even boundaries --- */
#define MPEG_WRITE_AUDIO16( address, value ) \
{ \
MPEG_WRITE_REGISTER( address , value ); \
MPEG_WRITE_REGISTER( address+1, value>>8 );\
}
#define MPEG_READ_AUDIO8( address, value ) \
{ \
MPEG_READ_REGISTER( address, value ); \
}
/* --- NOTE 16 bit quantities in the audio block are little endian and on even boundaries --- */
#define MPEG_READ_AUDIO16( address, value ) \
{ \
MPEG_READ_REGISTER( address+1, value ); \
value <<= 8; \
MPEG_READ_REGISTER( address, value ); \
}
/* --- NOTE 32 bit quantities in the audio block are little endian and on even boundaries
but THEY ARE NOT on word boundaries --- */
#define MPEG_READ_AUDIO32( address, value )\
{ \
MPEG_READ_REGISTER( address+3, value ); \
value <<= 8; \
MPEG_READ_REGISTER( address+2, value ); \
value <<= 8; \
MPEG_READ_REGISTER( address+1, value ); \
value <<= 8; \
MPEG_READ_REGISTER( address , value ); \
}
/* ============================================================================= */
/* VIDEO REGISTER MACRO */
/* ============================================================================= */
#define MPEG_WRITE_VIDEO8( address, value )\
{ \
MPEG_WRITE_REGISTER( address, value ); \
}
#define MPEG_WRITE_VIDEO16( address, value ) \
{ \
MPEG_WRITE_REGISTER( address, value>>8 ); \
MPEG_WRITE_REGISTER( address+1, value ); \
}
#define MPEG_READ_VIDEO8( address, value ) \
{ \
MPEG_READ_REGISTER( address, value ); \
}
#define MPEG_READ_VIDEO16(address, value) \
{ \
MPEG_READ_REGISTER(address, value); \
value <<= 8; \
MPEG_READ_REGISTER(address+1, value); \
}
#define MPEG_WRITE_VIDEO_2CYCLE(address, value) \
{ \
MPEG_WRITE_REGISTER(address, value>>8); \
MPEG_WRITE_REGISTER(address, value); \
}
#define MPEG_READ_VIDEO_2CYCLE( value ) __asm \
{ \
ldc 0xff; gintdis; \
ldc VID_HDF; /* Read [15:8] in first cycle */\
lb; \
ldc 8; \
shl; \
ldc VID_HDF; /* read [7:0] in next cycle */ \
lb; \
or; \
ld &value; /* store the 16 bit result */ \
ss; \
ldc 0xff; gintenb; \
}
/* ============================================================================= */
/* DENC REGISTER MACRO */
/* ============================================================================= */
#define MPEG_WRITE_DENC( address, value ) \
{ \
MPEG_WRITE_REGISTER( address, value ); \
}
#define MPEG_READ_DENC( address, value ) \
{ \
MPEG_READ_REGISTER( address, value ); \
}
#endif /* #ifndef _MPGIFACE_H_ */
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