swi_isr.s

Atmel AT91FR40162上的uCOS移植,该处理器内核为ARM7 TDMI

MAX_SWI_UCOS	EQU		5

	AREA  |subr|, CODE, READONLY

	INCLUDE parts/r40008/r40008.inc


;	IMPORT CRITICAL_NEST
	EXPORT SWI_ISR
	IMPORT SWI_Handler
	IMPORT __OSStartHighRdy
	IMPORT __OS_TASK_SW
;---------------------------------------------------------------------------
; SWI number assignment:
;	0	disable interrupt(enter critical)
;	1	enable interrupt (exit critical)
;	2	Start the highest priority ready task
;	3	Task level context switch
;	4	Switch to SYSTEM mode
;	5	Switch to USER mode
;	6	Disable FIQ
;	7	Enable FIQ
	ENTRY
SWI_ISR
	STMFD 	SP!, {R0-R1}
	MRS		R0, SPSR
	TST		R0, #T_BIT
	LDRNEH	R1, [LR,#-2]			;if in THUMB state...
	BICNE	R1, R1,#0xFF00			;if in THUMB state...
	LDREQ	R1, [LR,#-4]			;if in ARM state...
	BICEQ	R1, R1,#0XFF000000		;if in ARM state...
SWI_GET_SWI_INS
	CMP		R1,#MAX_SWI_UCOS
	LDRHI	R1,=MAX_SWI_UCOS+1
    ADR     R0, JUMP_TBL   			; Load address of jump table
    LDR     PC, [R0,R1,LSL#2]       ; Jump to the appropriate routine

JUMP_TBL
	DCD		SWI_ENTER_CRITICAL 	;0
	DCD		SWI_EXIT_CRITICAL	;1
	DCD		SWI_STARTHIGHRDY	;2
	DCD		SWI_OSCTXSW			;3
	DCD		SWI_EnterSysMode	;4
	DCD		SWI_EnterUserMode	;5
	DCD		SWI_DisableFIQ		;6
	DCD		SWI_EnableFIQ		;7
	DCD		SWI_Handler	

SWI_ENTER_CRITICAL
;	LDR		R0, =CRITICAL_NEST
;	LDR		R1,[R0]
;	ADD		R1,R1,#1
;	STR		R1,[R0]
	;
	MRS		R0, SPSR
  	ORR     R0, R0, #I_BIT    ;set the interrupt disable mode bit
  	MSR     SPSR_c, R0         
	LDMFD	SP!, {R0-R1}
	MOVS	PC,LR

SWI_EXIT_CRITICAL
;	LDR		R0, =CRITICAL_NEST
;	LDR		R1,[R0]
;	TEQ		R1,#0
;	BEQ		S_E_0
;	SUBS	R1,R1,#1
;	STR		R1,[R0]
;	LDMNEFD	SP!, {R0-R1}
;	MOVNES	PC,LR	   ;return if nest is not zero
;S_E_0
	;
	MRS		R0, SPSR
  	BIC     R0, R0, #I_BIT    ;set the interrupt disable mode bit
  	MSR     SPSR_c, R0         
	LDMFD	SP!, {R0-R1}
	MOVS	PC,LR

SWI_STARTHIGHRDY
;	LDR		R0, =CRITICAL_NEST
;	MOV		R1,#0
;	STR		R1,[R0]
	;
	LDMFD	SP!, {R0-R1}
	MSR		CPSR_c,#I_BIT :OR: ARM_MODE_SYS
	LDR		PC, =__OSStartHighRdy

SWI_OSCTXSW
	LDMFD	SP!, {R0-R1}
	LDR		PC, =__OS_TASK_SW

SWI_EnterSysMode
	MRS		R0, SPSR
	BIC		R0, R0, #0x1F
	ORR		R0, R0,#ARM_MODE_SYS
	MSR		SPSR_c, R0
	LDMFD	SP!, {R0-R1}
	MOVS	PC,LR

SWI_EnterUserMode
	MRS		R0, SPSR
	BIC		R0, R0, #0x1F
	ORR		R0, R0,#ARM_MODE_USER
	MSR		SPSR_c, R0
	LDMFD	SP!, {R0-R1}
	MOVS	PC,LR
SWI_DisableFIQ
	MRS		R0, SPSR
  	ORR     R0, R0, #F_BIT    ;set the FIQ disable mode bit
  	MSR     SPSR_c, R0         
	LDMFD	SP!, {R0-R1}
	MOVS	PC,LR

SWI_EnableFIQ
	MRS		R0, SPSR
  	BIC     R0, R0, #F_BIT    ;set the FIQ disable mode bit
  	MSR     SPSR_c, R0         
	LDMFD	SP!, {R0-R1}
	MOVS	PC,LR

	END
;---------------------------------------------------------------------------
END