os_cpu.h

Atmel AT91FR40162上的uCOS移植,该处理器内核为ARM7 TDMI

/*
*********************************************************************************************************
*                                               uC/OS-II
*                                        The Real-Time Kernel
*
*                        (c) Copyright 1992-1998, Jean J. Labrosse, Plantation, FL
*                                          All Rights Reserved
*                        (c) Copyright ARM Limited 1999.  All rights reserved.
*
*                                          ARM Specific code
*
* File : OS_CPU.H
*
* Modification : 21/08/00  EL
*********************************************************************************************************
*/

#include "periph\arm7tdmi\arm.h"

#ifdef  OS_CPU_GLOBALS
#define OS_CPU_EXT
#else
#define OS_CPU_EXT  extern
#endif

/*
*********************************************************************************************************
*                                              DATA TYPES
*                                         (Compiler Specific)
*********************************************************************************************************
*/

typedef unsigned char  BOOLEAN;
typedef unsigned char  INT8U;                    /* Unsigned  8 bit quantity                           */
typedef signed   char  INT8S;                    /* Signed    8 bit quantity                           */
typedef unsigned short INT16U;                   /* Unsigned 16 bit quantity                           */
typedef signed   short INT16S;                   /* Signed   16 bit quantity                           */
typedef unsigned long  INT32U;                   /* Unsigned 32 bit quantity                           */
typedef signed   long  INT32S;                   /* Signed   32 bit quantity                           */
typedef unsigned long long INT64U;
typedef signed long long INT64S;
typedef float          FP32;                     /* Single precision floating point                    */
typedef double         FP64;                     /* Double precision floating point                    */

//typedef unsigned int   OS_STK;                   /* Each stack entry is 16-bit wide                    */
typedef unsigned long   OS_STK;                   /* Each stack entry is 16-bit wide                    */

#define BYTE           INT8S                     /* Define data types for backward compatibility ...   */
#define UBYTE          INT8U                     /* ... to uC/OS V1.xx.  Not actually needed for ...   */
#define WORD           INT16S                    /* ... uC/OS-II.                                      */
#define UWORD          INT16U
#define LONG           INT32S
#define ULONG          INT32U

/* 
*********************************************************************************************************
*                              Intel 80x86 (Real-Mode, Large Model)
*
* Method #1:  Disable/Enable interrupts using simple instructions.  After critical section, interrupts
*             will be enabled even if they were disabled before entering the critical section.  You MUST
*             change the constant in OS_CPU_A.ASM, function OSIntCtxSw() from 10 to 8.
*
* Method #2:  Disable/Enable interrupts by preserving the state of interrupts.  In other words, if 
*             interrupts were disabled before entering the critical section, they will be disabled when
*             leaving the critical section.  You MUST change the constant in OS_CPU_A.ASM, function 
*             OSIntCtxSw() from 8 to 10.
*
* Method #3:  Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
*             would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
*             disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to 
*             disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
*             into the CPU's status register.
*********************************************************************************************************
*/
#define  OS_CRITICAL_METHOD    1
/*
*********************************************************************************************************
*                              ARM, various architectures
*
*********************************************************************************************************
*/
//#define OS_ENTER_CRITICAL() ARMDisableInt()      //use this pair to globally disable interrupts
//#define OS_EXIT_CRITICAL()  ARMEnableInt()       //cation - ArmenableInt re-enables interrupts ready or not
//#define OS_ENTER_CRITICAL() {if(ARMIntNesting == 0) __asm{swi 0}}      //use this pair to globally disable interrupts
//#define OS_EXIT_CRITICAL()  {if(ARMIntNesting == 0) __asm{swi 1};}       //cation - ArmenableInt re-enables interrupts ready or not
#define OS_ENTER_CRITICAL() {if(OSIntNesting == 0) __asm{swi 0}}      //use this pair to globally disable interrupts
#define OS_EXIT_CRITICAL()  {if(OSIntNesting == 0) __asm{swi 1};}       //cation - ArmenableInt re-enables interrupts ready or not
#define OSStartHighRdy() {__asm{swi 2}}

#define DN_FIQ() {__asm{swi 6}}
#define EN_FIQ() {__asm{swi 7}}

/* stack stuff */
#define OS_STK_GROWTH    1         //define the stack to grow from high to low


/* idle task stack size (words) */
#ifdef SEMIHOSTED
#define OS_IDLE_STK_SIZE        (64+SEMIHOSTED_STACK_NEEDS)
#else
#define OS_IDLE_STK_SIZE        64
#endif


/* defined in os_cpu_a.s */
//extern void OS_TASK_SW(void);           // task switch routine
#define OS_TASK_SW() {__asm{swi 3}}
extern void OSIntCtxSw(void);           // interrupt context switch
extern void ARMDisableInt(void);        // disable global interrupts
extern void ARMEnableInt(void);         // enable global interrupts
extern void OSTickISR(void);		// timer interrupt routine