📄 cstartup_sam7.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.30A/W32 KICKSTART 31/Oct/2005 17:17:33 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\SrcIAR\Cstar #
# tup_SAM7.c #
# Command line = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\SrcIAR\Cstar #
# tup_SAM7.c -D ESS -lC E:\SAM7X\AT91_SAM7X256-IAR\AT9 #
# 1SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7X256-BasicEm #
# ac\compil\bin\List\ -o E:\SAM7X\AT91_SAM7X256-IAR\AT #
# 91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7X256-BasicE #
# mac\compil\bin\Obj\ -z3 --no_cse --no_unroll #
# --no_inline --no_code_motion --no_tbaa #
# --no_clustering --no_scheduling --debug --cpu_mode #
# thumb --endian little --cpu ARM7TDMI --stack_align #
# 4 --interwork -e --fpu None --dlib_config #
# "D:\Program Files\IAR Systems\Embedded Workbench #
# 4.0 Kickstart\arm\LIB\dl4tptinl8n.h" -I #
# E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\..\..\ -I #
# E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\srcIAR\ -I #
# "D:\Program Files\IAR Systems\Embedded Workbench #
# 4.0 Kickstart\arm\INC\" #
# List file = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\bin\List\Cst #
# artup_SAM7.lst #
# Object file = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\bin\Obj\Csta #
# rtup_SAM7.r79 #
# #
# #
##############################################################################
E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7X256-BasicEmac\compil\SrcIAR\Cstartup_SAM7.c
1 //*----------------------------------------------------------------------------
2 //* ATMEL Microcontroller Software Support - ROUSSET -
3 //*----------------------------------------------------------------------------
4 //* The software is delivered "AS IS" without warranty or condition of any
5 //* kind, either express, implied or statutory. This includes without
6 //* limitation any warranty or condition with respect to merchantability or
7 //* fitness for any particular purpose, or against the infringements of
8 //* intellectual property rights of others.
9 //*----------------------------------------------------------------------------
10 //* File Name : Cstartup_SAM7.c
11 //* Object : Low level initializations written in C for IAR
12 //* tools
13 //* 1.0 08/Sep/04 JPP : Creation
14 //* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
15 //*----------------------------------------------------------------------------
16
17 // Include the board file description
18 #include "Board.h"
19 #include <string.h>
20
21 extern void AT91F_DBGU_Printk(char *);
22 // The following functions must be write in ARM mode this function called directly
23 // by exception vector
24 extern void AT91F_Spurious_handler(void);
25 extern void AT91F_Default_IRQ_handler(void);
26 extern void AT91F_Default_FIQ_handler(void);
27
28
29 //*----------------------------------------------------------------------------
30 //* \fn AT91F_LowLevelInit
31 //* \brief This function performs very low level HW initialization
32 //* this function can be use a Stack, depending the compilation
33 //* optimization mode
34 //*----------------------------------------------------------------------------
\ In segment ICODE, align 4, keep-with-next
35 void AT91F_LowLevelInit( void) @ "ICODE"
36 {
\ AT91F_LowLevelInit:
\ 00000000 00B5 PUSH {LR}
37 int i;
38 AT91PS_PMC pPMC = AT91C_BASE_PMC;
\ 00000002 1848 LDR R0,??AT91F_LowLevelInit_0 ;; 0xfffffc00
39
40 // Set Flash Waite sate
41 // Single Cycle Access at Up to 30 MHz, or 40
42 // if MCK = 47923200 I have 75 Cycle for 1.5 useconde ( flied MC_FMR->FMCN
43 AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
\ 00000004 9F21 MOV R1,#+0x9F
\ 00000006 C943 MVN R1,R1 ;; #-160
\ 00000008 174A LDR R2,??AT91F_LowLevelInit_0+0x4 ;; 0x4b0100
\ 0000000A 0A60 STR R2,[R1, #+0]
44
45 // Watchdog Disable
46 AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
\ 0000000C 1749 LDR R1,??AT91F_LowLevelInit_0+0x8 ;; 0xfffffd44
\ 0000000E 8022 MOV R2,#+0x80
\ 00000010 1202 LSL R2,R2,#+0x8 ;; #+0x8000
\ 00000012 0A60 STR R2,[R1, #+0]
47
48 // Set MCK at 47 923 200
49
50 // 1 Enabling the Main Oscillator:
51 // SCK = 1/32768 = 30.51 uSeconde
52 // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
53 pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
\ 00000014 1649 LDR R1,??AT91F_LowLevelInit_0+0xC ;; 0x601
\ 00000016 0162 STR R1,[R0, #+0x20]
54
55 // Wait the startup time
56 while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
\ ??AT91F_LowLevelInit_1:
\ 00000018 816E LDR R1,[R0, #+0x68]
\ 0000001A C907 LSL R1,R1,#+0x1F
\ 0000001C FCD5 BPL ??AT91F_LowLevelInit_1
57
58 // 2 Checking the Main Oscillator Frequency (Optional)
59
60 // 3 Setting PLL and divider:
61 // - div by 5 Fin = 3,6864 =(18,432 / 5)
62 // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
63 // for 96 MHz the erroe is 0.16%
64 //eld out NOT USED = 0 Fi
65 pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
66 (AT91C_CKGR_PLLCOUNT & (28<<8)) |
67 (AT91C_CKGR_MUL & (25<<16)));
\ 0000001E 1549 LDR R1,??AT91F_LowLevelInit_0+0x10 ;; 0x191c05
\ 00000020 C162 STR R1,[R0, #+0x2C]
68
69 // Wait the startup time
70 while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
\ ??AT91F_LowLevelInit_2:
\ 00000022 816E LDR R1,[R0, #+0x68]
\ 00000024 4907 LSL R1,R1,#+0x1D
\ 00000026 FCD5 BPL ??AT91F_LowLevelInit_2
71
72 // 4. Selection of Master Clock and Processor Clock
73 // select the PLL clock divided by 2
74 pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
\ 00000028 0421 MOV R1,#+0x4
\ 0000002A 0163 STR R1,[R0, #+0x30]
75 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??AT91F_LowLevelInit_3:
\ 0000002C 816E LDR R1,[R0, #+0x68]
\ 0000002E 0907 LSL R1,R1,#+0x1C
\ 00000030 FCD5 BPL ??AT91F_LowLevelInit_3
76
77 pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
\ 00000032 016B LDR R1,[R0, #+0x30]
\ 00000034 0322 MOV R2,#+0x3
\ 00000036 0A43 ORR R2,R1
\ 00000038 0263 STR R2,[R0, #+0x30]
78 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??AT91F_LowLevelInit_4:
\ 0000003A 816E LDR R1,[R0, #+0x68]
\ 0000003C 0907 LSL R1,R1,#+0x1C
\ 0000003E FCD5 BPL ??AT91F_LowLevelInit_4
79
80 // Set up the default interrupts handler vectors
81 AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
\ 00000040 0D48 LDR R0,??AT91F_LowLevelInit_0+0x14 ;; 0xfffff080
\ 00000042 0E49 LDR R1,??AT91F_LowLevelInit_0+0x18 ;; AT91F_Default_FIQ_handler
\ 00000044 0160 STR R1,[R0, #+0]
82 for (i=1;i < 31; i++)
\ 00000046 0120 MOV R0,#+0x1
\ 00000048 05E0 B ??AT91F_LowLevelInit_5
83 {
84 AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
\ ??AT91F_LowLevelInit_6:
\ 0000004A 0421 MOV R1,#+0x4
\ 0000004C 4143 MUL R1,R0
\ 0000004E 0A4A LDR R2,??AT91F_LowLevelInit_0+0x14 ;; 0xfffff080
\ 00000050 0B4B LDR R3,??AT91F_LowLevelInit_0+0x1C ;; AT91F_Default_IRQ_handler
\ 00000052 5350 STR R3,[R2, R1]
85 }
\ 00000054 401C ADD R0,#+0x1
\ ??AT91F_LowLevelInit_5:
\ 00000056 1F28 CMP R0,#+0x1F
\ 00000058 F7DB BLT ??AT91F_LowLevelInit_6
86 AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
\ 0000005A 0A48 LDR R0,??AT91F_LowLevelInit_0+0x20 ;; 0xfffff134
\ 0000005C 0A49 LDR R1,??AT91F_LowLevelInit_0+0x24 ;; AT91F_Spurious_handler
\ 0000005E 0160 STR R1,[R0, #+0]
87 }
\ 00000060 01BC POP {R0}
\ 00000062 0047 BX R0 ;; return
\ ??AT91F_LowLevelInit_0:
\ 00000064 00FCFFFF DC32 0xfffffc00
\ 00000068 00014B00 DC32 0x4b0100
\ 0000006C 44FDFFFF DC32 0xfffffd44
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