📄 emac.lst
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159 read_phy(pEmac, AT91C_PHY_ADDR, MII_PHYSID1, &phyid1);
\ 0000000C 01AB ADD R3,SP,#+0x4
\ 0000000E 0222 MOV R2,#+0x2
\ 00000010 1F21 MOV R1,#+0x1F
\ 00000012 201C MOV R0,R4
\ 00000014 ........ BL read_phy
160 read_phy(pEmac, AT91C_PHY_ADDR, MII_PHYSID2, &phyid2);
\ 00000018 6B46 MOV R3,SP
\ 0000001A 0322 MOV R2,#+0x3
\ 0000001C 1F21 MOV R1,#+0x1F
\ 0000001E 201C MOV R0,R4
\ 00000020 ........ BL read_phy
161
162 /* AMD AM79C875: PHY_ID1 = 0x0022 PHY_ID2 = 0x5541
163 Bits 3:0 Revision Number Four bit manufacturer抯 revision number. 0001 stands for Rev. A, etc.
164 These bits are masked.
165 */
166 if (((phyid1 << 16) | (phyid2 & 0xfff0)) != MII_DM9161_ID) {
\ 00000024 0198 LDR R0,[SP, #+0x4]
\ 00000026 0004 LSL R0,R0,#+0x10
\ 00000028 0099 LDR R1,[SP, #+0]
\ 0000002A 0C4A LDR R2,??AT91F_Ether_Probe_0 ;; 0xfff0
\ 0000002C 0A40 AND R2,R1
\ 0000002E 0243 ORR R2,R0
\ 00000030 0B48 LDR R0,??AT91F_Ether_Probe_0+0x4 ;; 0x181b8a0
\ 00000032 8242 CMP R2,R0
\ 00000034 05D0 BEQ ??AT91F_Ether_Probe_1
167 AT91F_Disable_Mdi(pEmac);
\ 00000036 201C MOV R0,R4
\ 00000038 ........ BL AT91F_Disable_Mdi
168 return -1;
\ 0000003C 0020 MOV R0,#+0
\ 0000003E C043 MVN R0,R0 ;; #-1
\ 00000040 07E0 B ??AT91F_Ether_Probe_2
169 }
170 status = AT91F_GetLinkSpeed(pEmac);
\ ??AT91F_Ether_Probe_1:
\ 00000042 201C MOV R0,R4
\ 00000044 ........ BL AT91F_GetLinkSpeed
\ 00000048 051C MOV R5,R0
171 AT91F_Disable_Mdi(pEmac);
\ 0000004A 201C MOV R0,R4
\ 0000004C ........ BL AT91F_Disable_Mdi
172 return status;
\ 00000050 281C MOV R0,R5
\ ??AT91F_Ether_Probe_2:
\ 00000052 02B0 ADD SP,#+0x8
\ 00000054 30BC POP {R4,R5}
\ 00000056 02BC POP {R1}
\ 00000058 0847 BX R1 ;; return
\ 0000005A C046 NOP
\ ??AT91F_Ether_Probe_0:
\ 0000005C F0FF0000 DC32 0xfff0
\ 00000060 A0B88101 DC32 0x181b8a0
173 }
174
175
176
177 //*----------------------------------------------------------------------------
178 //* \fn AT91F_EMACInit
179 //* \brief This function initialise the ethernet
180 //*----------------------------------------------------------------------------
\ In segment CODE, align 4, keep-with-next
181 int AT91F_EMACInit( // \return Status ( Success = 0)
182 AT91PS_EMAC pEmac, // \arg Pointer to AT91PS_EMAC service
183 unsigned int pRxTdList,
184 unsigned int pTxTdList)
185 {
\ AT91F_EMACInit:
\ 00000000 70B5 PUSH {R4-R6,LR}
\ 00000002 041C MOV R4,R0
\ 00000004 0D1C MOV R5,R1
\ 00000006 161C MOV R6,R2
186 if (AT91F_Ether_Probe(pEmac))
\ 00000008 201C MOV R0,R4
\ 0000000A ........ BL AT91F_Ether_Probe
\ 0000000E 0028 CMP R0,#+0
\ 00000010 02D0 BEQ ??AT91F_EMACInit_0
187 return -1;
\ 00000012 0020 MOV R0,#+0
\ 00000014 C043 MVN R0,R0 ;; #-1
\ 00000016 24E0 B ??AT91F_EMACInit_1
188
189 // the sequence write EMAC_SA1L and write EMAC_SA1H must be respected
190 pEmac->EMAC_SA1L = ((int)OurEmacAddr[3] << 24) | ((int)OurEmacAddr[2] << 16) | ((int)OurEmacAddr[1] << 8) | OurEmacAddr[0];
\ ??AT91F_EMACInit_0:
\ 00000018 9820 MOV R0,#+0x98
\ 0000001A 1349 LDR R1,??AT91F_EMACInit_2 ;; OurEmacAddr + 3
\ 0000001C 0978 LDRB R1,[R1, #+0]
\ 0000001E 0A06 LSL R2,R1,#+0x18
\ 00000020 1249 LDR R1,??AT91F_EMACInit_2+0x4 ;; OurEmacAddr + 2
\ 00000022 0978 LDRB R1,[R1, #+0]
\ 00000024 0904 LSL R1,R1,#+0x10
\ 00000026 1143 ORR R1,R2
\ 00000028 114A LDR R2,??AT91F_EMACInit_2+0x8 ;; OurEmacAddr + 1
\ 0000002A 1278 LDRB R2,[R2, #+0]
\ 0000002C 1202 LSL R2,R2,#+0x8
\ 0000002E 0A43 ORR R2,R1
\ 00000030 .... LDR R1,??DataTable0 ;; OurEmacAddr
\ 00000032 0978 LDRB R1,[R1, #+0]
\ 00000034 1143 ORR R1,R2
\ 00000036 2150 STR R1,[R4, R0]
191 pEmac->EMAC_SA1H = ((int)OurEmacAddr[5] << 8) | OurEmacAddr[4];
\ 00000038 9C20 MOV R0,#+0x9C
\ 0000003A 0E49 LDR R1,??AT91F_EMACInit_2+0xC ;; OurEmacAddr + 5
\ 0000003C 0978 LDRB R1,[R1, #+0]
\ 0000003E 0902 LSL R1,R1,#+0x8
\ 00000040 0D4A LDR R2,??AT91F_EMACInit_2+0x10 ;; OurEmacAddr + 4
\ 00000042 1278 LDRB R2,[R2, #+0]
\ 00000044 0A43 ORR R2,R1
\ 00000046 2250 STR R2,[R4, R0]
192
193 pEmac->EMAC_RBQP = pRxTdList;
\ 00000048 A561 STR R5,[R4, #+0x18]
194 pEmac->EMAC_TBQP = pTxTdList;
\ 0000004A E661 STR R6,[R4, #+0x1C]
195
196 //Clear receive status register
197 pEmac->EMAC_RSR = (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
\ 0000004C 0720 MOV R0,#+0x7
\ 0000004E 2062 STR R0,[R4, #+0x20]
198 pEmac->EMAC_NCFGR |= (AT91C_EMAC_CAF | AT91C_EMAC_NBC );// | AT91C_EMAC_RBOF_OFFSET_2);
\ 00000050 6068 LDR R0,[R4, #+0x4]
\ 00000052 3021 MOV R1,#+0x30
\ 00000054 0143 ORR R1,R0
\ 00000056 6160 STR R1,[R4, #+0x4]
199
200 pEmac->EMAC_NCR |= (AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT);
\ 00000058 2068 LDR R0,[R4, #+0]
\ 0000005A 8C21 MOV R1,#+0x8C
\ 0000005C 0143 ORR R1,R0
\ 0000005E 2160 STR R1,[R4, #+0]
201
202 return 0;
\ 00000060 0020 MOV R0,#+0
\ ??AT91F_EMACInit_1:
\ 00000062 70BC POP {R4-R6}
\ 00000064 02BC POP {R1}
\ 00000066 0847 BX R1 ;; return
\ ??AT91F_EMACInit_2:
\ 00000068 ........ DC32 OurEmacAddr + 3
\ 0000006C ........ DC32 OurEmacAddr + 2
\ 00000070 ........ DC32 OurEmacAddr + 1
\ 00000074 ........ DC32 OurEmacAddr + 5
\ 00000078 ........ DC32 OurEmacAddr + 4
203 }
204
205 #define AT91C_RCV_OFFSET 0
206
207 //*----------------------------------------------------------------------------
208 //* \fn AT91F_EmacEntry
209 //* \brief Initialise Emac to receive packets
210 //*----------------------------------------------------------------------------
\ In segment CODE, align 4, keep-with-next
211 int AT91F_EmacEntry(void)
212 {
\ AT91F_EmacEntry:
\ 00000000 10B5 PUSH {R4,LR}
213 unsigned int i;
214 unsigned int val;
215
216 // Initialise RxtdList descriptor
217 for (i = 0; i < NB_RX_BUFFERS; ++i) {
\ 00000002 0020 MOV R0,#+0
\ 00000004 13E0 B ??AT91F_EmacEntry_0
218 val = (unsigned int)(RxPacket + (i * ETH_RX_BUFFER_SIZE));
\ ??AT91F_EmacEntry_1:
\ 00000006 8021 MOV R1,#+0x80
\ 00000008 4143 MUL R1,R0
\ 0000000A 264A LDR R2,??AT91F_EmacEntry_2 ;; RxPacket
\ 0000000C 1268 LDR R2,[R2, #+0]
\ 0000000E 5118 ADD R1,R2,R1
219 RxtdList[i].addr = val & 0xFFFFFFF8;
\ 00000010 0822 MOV R2,#+0x8
\ 00000012 4243 MUL R2,R0
\ 00000014 .... LDR R3,??DataTable10 ;; RxtdList
\ 00000016 1B68 LDR R3,[R3, #+0]
\ 00000018 0724 MOV R4,#+0x7
\ 0000001A A143 BIC R1,R4
\ 0000001C 9950 STR R1,[R3, R2]
220 RxtdList[i].U_Status.status = 0;
\ 0000001E 0821 MOV R1,#+0x8
\ 00000020 4143 MUL R1,R0
\ 00000022 .... LDR R2,??DataTable10 ;; RxtdList
\ 00000024 1268 LDR R2,[R2, #+0]
\ 00000026 5118 ADD R1,R2,R1
\ 00000028 0022 MOV R2,#+0
\ 0000002A 4A60 STR R2,[R1, #+0x4]
221 }
\ 0000002C 401C ADD R0,#+0x1
\ ??AT91F_EmacEntry_0:
\ 0000002E 6428 CMP R0,#+0x64
\ 00000030 E9D3 BCC ??AT91F_EmacEntry_1
222 // Set the WRAP bit at the end of the list descriptor
223 RxtdList[NB_RX_BUFFERS-1].addr |= 0x02;
\ 00000032 C620 MOV R0,#+0xC6
\ 00000034 8000 LSL R0,R0,#+0x2 ;; #+0x318
\ 00000036 .... LDR R1,??DataTable10 ;; RxtdList
\ 00000038 0968 LDR R1,[R1, #+0]
\ 0000003A C622 MOV R2,#+0xC6
\ 0000003C 9200 LSL R2,R2,#+0x2 ;; #+0x318
\ 0000003E .... LDR R3,??DataTable10 ;; RxtdList
\ 00000040 1B68 LDR R3,[R3, #+0]
\ 00000042 9A58 LDR R2,[R3, R2]
\ 00000044 0223 MOV R3,#+0x2
\ 00000046 1343 ORR R3,R2
\ 00000048 0B50 STR R3,[R1, R0]
224
225 // Initialise TxtdList descriptor
226 for (i = 0; i < NB_TX_BUFFERS; ++i) {
\ 0000004A 0020 MOV R0,#+0
\ 0000004C 14E0 B ??AT91F_EmacEntry_3
227 val = (unsigned int)(TxPacket + (i * ETH_TX_BUFFER_SIZE));
\ ??AT91F_EmacEntry_4:
\ 0000004E C021 MOV R1,#+0xC0
\ 00000050 C900 LSL R1,R1,#+0x3 ;; #+0x600
\ 00000052 4143 MUL R1,R0
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