📄 emac.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.30A/W32 KICKSTART 31/Oct/2005 17:17:34 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\src\Emac.c #
# Command line = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\src\Emac.c -D ESS #
# -lC E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMA #
# C_IAR4_30-1_2\AT91SAM7X256-BasicEmac\compil\bin\List #
# \ -o E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEM #
# AC_IAR4_30-1_2\AT91SAM7X256-BasicEmac\compil\bin\Obj #
# \ -z3 --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --cpu_mode thumb --endian #
# little --cpu ARM7TDMI --stack_align 4 --interwork #
# -e --fpu None --dlib_config "D:\Program Files\IAR #
# Systems\Embedded Workbench 4.0 #
# Kickstart\arm\LIB\dl4tptinl8n.h" -I #
# E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\..\..\ -I #
# E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\srcIAR\ -I #
# "D:\Program Files\IAR Systems\Embedded Workbench #
# 4.0 Kickstart\arm\INC\" #
# List file = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\bin\List\Ema #
# c.lst #
# Object file = E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IA #
# R4_30-1_2\AT91SAM7X256-BasicEmac\compil\bin\Obj\Emac #
# .r79 #
# #
# #
##############################################################################
E:\SAM7X\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7X256-BasicEmac\src\Emac.c
1 //*----------------------------------------------------------------------------
2 //* ATMEL Microcontroller Software Support - ROUSSET -
3 //*----------------------------------------------------------------------------
4 //* The software is delivered "AS IS" without warranty or condition of any
5 //* kind, either express, implied or statutory. This includes without
6 //* limitation any warranty or condition with respect to merchantability or
7 //* fitness for any particular purpose, or against the infringements of
8 //* intellectual property rights of others.
9 //*----------------------------------------------------------------------------
10 //* File Name : main.c
11 //* Object : main application written in C
12 //* Creation : Hi 11/18/2002
13 //* Update : JGe 08/02/2005 : SAM7X port
14 //*----------------------------------------------------------------------------
15
16 #include "board.h"
17 #include "Emac.h"
18 #include "mii.h"
19 #include <string.h>
20 #include <stdio.h>
21
22 //extern unsigned int AT91F_GetTickCount(void);
23 extern void AT91F_DBGU_Printk(char *buffer);
24 extern void AT91F_DisplayIpPacket(AT91PS_IPheader pIpHeader);
25 extern char MsgBuffer[256];
26 extern int AT91F_ProcessEmacPacket(AT91PS_IPheader pHeader);
27 extern void LED_TurnOn(unsigned int led);
28 extern void LED_TurnOff(unsigned int led);
29
30 // Our Ethernet MAC address and IP address
\ In segment DATA_I, align 4, align-sorted
31 char OurEmacAddr[6] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06};
\ OurEmacAddr:
\ 00000000 DS8 8
\ 00000008 REQUIRE `?<Initializer for OurEmacAddr>`
32 //unsigned char OurIpAddr[4] = {10, 159, 245, 183}; // {0x0A, 0xD7, 0xF5, 0xAC}
\ In segment DATA_I, align 4, align-sorted
33 unsigned char OurIpAddr[4] = {192, 168, 0, 21}; // {0x0A, 0xD7, 0xF5, 0xAC}
\ OurIpAddr:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for OurIpAddr>`
34
35 //Buffer descriptor address must be word aligned
36 #define AT91C_EMAC_RX_TDLIST_BASE 0x00204000 // take care that RxtdList[NB_RCV_BUFFERS] area is available
37 #define AT91C_EMAC_TX_TDLIST_BASE (AT91C_EMAC_RX_TDLIST_BASE + NB_RX_BUFFERS * sizeof(AT91S_RxTdDescriptor))
38 #define AT91C_EMAC_RX_PACKET_BASE (AT91C_EMAC_TX_TDLIST_BASE + NB_TX_BUFFERS * sizeof(AT91S_TxTdDescriptor))
39 #define AT91C_EMAC_TX_PACKET_BASE (AT91C_EMAC_RX_PACKET_BASE + NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE)
40
\ In segment DATA_I, align 4, align-sorted
41 char *RxPacket = (char *)AT91C_EMAC_RX_PACKET_BASE;
\ RxPacket:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for RxPacket>`
\ In segment DATA_I, align 4, align-sorted
42 char *TxPacket = (char *)AT91C_EMAC_TX_PACKET_BASE;
\ TxPacket:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for TxPacket>`
\ In segment DATA_I, align 4, align-sorted
43 AT91PS_RxTdDescriptor RxtdList = (AT91PS_RxTdDescriptor) AT91C_EMAC_RX_TDLIST_BASE;
\ RxtdList:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for RxtdList>`
\ In segment DATA_I, align 4, align-sorted
44 AT91PS_TxTdDescriptor TxtdList = (AT91PS_TxTdDescriptor)AT91C_EMAC_TX_TDLIST_BASE;
\ TxtdList:
\ 00000000 DS8 4
\ 00000004 REQUIRE `?<Initializer for TxtdList>`
45
\ In segment DATA_Z, align 4, align-sorted
46 unsigned int TxBuffIndex = 0;
\ TxBuffIndex:
\ 00000000 DS8 4
47
48 // mapping
49 // 0x00204000 - 0x0020431F : RX descriptor list : 800 bytes
50 // 0x00204320 - 0x0020432F : TX descriptor list : 16 bytes
51 // 0x00204330 - 0x0020752F : RX packets : 12800 bytes
52 // 0x00207530 - 0x0020762F : TX packets : 256 bytes
53
54 // ****************************************************************************************************
55 // ** EMAC lowlevel functions
56 // ****************************************************************************************************
57
58 // Enable the MDIO bit in MAC control register
\ In segment CODE, align 4, keep-with-next
59 void AT91F_Enable_Mdi(AT91PS_EMAC pEmac)
60 {
61 pEmac->EMAC_NCR |= AT91C_EMAC_MPE; // enable management port
\ AT91F_Enable_Mdi:
\ 00000000 0168 LDR R1,[R0, #+0]
\ 00000002 1022 MOV R2,#+0x10
\ 00000004 0A43 ORR R2,R1
\ 00000006 0260 STR R2,[R0, #+0]
62 pEmac->EMAC_NCFGR |= (2)<<10; // MDC = MCK/32
\ 00000008 4168 LDR R1,[R0, #+0x4]
\ 0000000A 8022 MOV R2,#+0x80
\ 0000000C 1201 LSL R2,R2,#+0x4 ;; #+0x800
\ 0000000E 0A43 ORR R2,R1
\ 00000010 4260 STR R2,[R0, #+0x4]
63 }
\ 00000012 7047 BX LR ;; return
64
65 // Disable the MDIO bit in the MAC control register
\ In segment CODE, align 4, keep-with-next
66 void AT91F_Disable_Mdi(AT91PS_EMAC pEmac)
67 {
68 pEmac->EMAC_NCR &= ~AT91C_EMAC_MPE; // disable management port
\ AT91F_Disable_Mdi:
\ 00000000 0168 LDR R1,[R0, #+0]
\ 00000002 1022 MOV R2,#+0x10
\ 00000004 9143 BIC R1,R2
\ 00000006 0160 STR R1,[R0, #+0]
69 }
\ 00000008 7047 BX LR ;; return
70
71 // Write value to the a PHY register
72 // Note: MDI interface is assumed to already have been enabled.
\ In segment CODE, align 4, keep-with-next
73 void write_phy(AT91PS_EMAC pEmac, unsigned char phy_addr, unsigned char address, unsigned int value)
74 {
75 pEmac->EMAC_MAN = ((AT91C_EMAC_SOF & (0x01<<30)) | (2 << 16) | (1 << 28)
76 | ((phy_addr & 0x1f) << 23) | (address << 18)) | (value & 0xffff);
\ write_phy:
\ 00000000 C906 LSL R1,R1,#+0x1B ;; ZeroExt R1,R1,#+0x1B,#+0x1B
\ 00000002 C90E LSR R1,R1,#+0x1B
\ 00000004 C905 LSL R1,R1,#+0x17
\ 00000006 9204 LSL R2,R2,#+0x12
\ 00000008 0A43 ORR R2,R1
\ 0000000A 1904 LSL R1,R3,#+0x10 ;; ZeroExt R1,R3,#+0x10,#+0x10
\ 0000000C 090C LSR R1,R1,#+0x10
\ 0000000E 1143 ORR R1,R2
\ 00000010 034A LDR R2,??write_phy_0 ;; 0x50020000
\ 00000012 0A43 ORR R2,R1
\ 00000014 4263 STR R2,[R0, #+0x34]
77
78 /* Wait until IDLE bit in Network Status register is cleared */
79 while (!(pEmac->EMAC_NSR & AT91C_EMAC_IDLE));
\ ??write_phy_1:
\ 00000016 8168 LDR R1,[R0, #+0x8]
\ 00000018 4907 LSL R1,R1,#+0x1D
\ 0000001A FCD5 BPL ??write_phy_1
80 }
\ 0000001C 7047 BX LR ;; return
\ 0000001E C046 NOP
\ ??write_phy_0:
\ 00000020 00000250 DC32 0x50020000
81
82 // Read value stored in a PHY register.
83 // Note: MDI interface is assumed to already have been enabled.
\ In segment CODE, align 4, keep-with-next
84 void read_phy(AT91PS_EMAC pEmac, unsigned char phy_addr, unsigned char address, unsigned int *value)
85 {
86 pEmac->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30)) | (2 << 16) | (2 << 28)
87 | ((phy_addr & 0x1f) << 23) | (address << 18);
\ read_phy:
\ 00000000 C906 LSL R1,R1,#+0x1B ;; ZeroExt R1,R1,#+0x1B,#+0x1B
\ 00000002 C90E LSR R1,R1,#+0x1B
\ 00000004 C905 LSL R1,R1,#+0x17
\ 00000006 9204 LSL R2,R2,#+0x12
\ 00000008 0A43 ORR R2,R1
\ 0000000A 0549 LDR R1,??read_phy_0 ;; 0x60020000
\ 0000000C 1143 ORR R1,R2
\ 0000000E 4163 STR R1,[R0, #+0x34]
88
89 /* Wait until IDLE bit in Network Status register is cleared */
90 while (!(pEmac->EMAC_NSR & AT91C_EMAC_IDLE));
\ ??read_phy_1:
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