gpmmp.inc

AMI 主板的BIOS源码

subttl.	Include file for DUAL/MULTIPROCESSOR support SMI handling code....GPMMP.INC

;-----------------------------------------------;
;  FOLLOWING ROUTINES USED FROM OTHER MODULES	;
;-----------------------------------------------;

;;	public	save_and_mask_apic_intr		;
;;	public	restore_and_unmask_apic_intr	;

;;	public	setup_smi_handler_for_multiple_cpu
;;	public	relocate_smbase_for_multiple_cpu;

;-----------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;**								**;
;**	(C)Copyright 1985-1996, American Megatrends Inc.	**;
;**								**;
;**			All Rights Reserved.			**;
;**								**;
;**		6145-F, Northbelt Parkway, Norcross,		**;
;**								**;
;**		Georgia - 30071, USA. Phone-(770)-246-8600.	**;
;**								**;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------------------------------;
;	    THIS PORTION OF CODE SUPPORTS INTEL APIC		;
;	    MULTIPROCESSOR SMI BASED POWER MANAGEMENT		;
;---------------------------------------------------------------;

IF	INTEL_APIC_MP_SUPPORT

intel_mp_smi_handler	label	byte

;---------------------------------------------------------------;
;    RUN TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;    RUN TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;    RUN TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;    RUN TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;---------------------------------------------------------------;
; All the code from here labelled as 'NON_BSP_SMI_CODE_BEGIN' to;
; the label 'NON_BSP_SMI_CODE_END' will be copied to the smram. ;
; This code will execute in smram during the handling of smi.	;
; Please make sure that any code needed during smi handler should
; be added after the label 'NON_BSP_SMI_CODE_BEGIN' and before	;
; the label 'NON_BSP_SMI_CODE_END'.				;
;---------------------------------------------------------------;
;			  ORG 8000H				;
;---------------------------------------------------------------;

non_bsp_smi_code_begin	label	byte

	include	gpmmp.css			; DUAL/MULTIPROCESSOR SMI handling code

;---------------------------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;**								**;
;**	(C)Copyright 1985-1996, American Megatrends Inc.	**;
;**								**;
;**			All Rights Reserved.			**;
;**								**;
;**		6145-F, Northbelt Parkway, Norcross,		**;
;**								**;
;**		Georgia - 30071, USA. Phone-(770)-246-8600.	**;
;**								**;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------------------------------;
;	   RUN TIME CORE BIOS BSP APIC SAVE/RESTORE CODE	;
;	   RUN TIME CORE BIOS BSP APIC SAVE/RESTORE CODE	;
;	   RUN TIME CORE BIOS BSP APIC SAVE/RESTORE CODE	;
;	   RUN TIME CORE BIOS BSP APIC SAVE/RESTORE CODE	;
;---------------------------------------------------------------;
;		    SAVE_AND_MASK_APIC_INTR			;
;---------------------------------------------------------------;
;	Input : (DS) PM BIOS data segment			;
;		STACK PRESENT					;
;	Output: NONE						;
;	Register destroyed : NONE				;
; NOTE :							;
;  * This will mask all interrupts generated thru local APIC	;
;    of INTEL PENTIUM processor.				;
;  * (ES) has 4 GB limit at this point				;
;  * This routine should be used with BSP processor only	;
;---------------------------------------------------------------;

save_and_mask_apic_intr	proc	near

	push	es				;
	push	eax				;
	push	esi				;
	push	di				;

	push	0000h				;
	pop	es				; set (es) to 0000h to access 4 GB address space

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_lvt_timer_reg		; (esi) = APIC local vector table reg for TIMER (0FEE0_0320H)
	mov	di,apic_lvt_timer_reg_save_area	; (di) = APIC local vector table for TIMER save area
	call	save_mask_apic_local_vec_tbl	; save and mask APIC local interrupt

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_lvt_intr_00_reg		; (esi) = APIC local vector table reg for LINT0 (0FEE0_0350H)
	mov	di,apic_lvt_intr_00_reg_save_area; (di) = APIC local vector table for LINT0 save area
	call	save_mask_apic_local_vec_tbl	; save and mask APIC local interrupt

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_lvt_intr_01_reg		; (esi) = APIC local vector table reg for LINT1 (0FEE0_0360H)
	mov	di,apic_lvt_intr_01_reg_save_area; (di) = APIC local vector table for LINT1 save area
	call	save_mask_apic_local_vec_tbl	; save and mask APIC local interrupt

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_lvt_err_reg		; (esi) = APIC local vector table reg for ERROR (0FEE0_0370H)
	mov	di,apic_lvt_err_reg_save_area	; (di) = APIC local vector table for ERROR save area
	call	save_mask_apic_local_vec_tbl	; save and mask APIC local interrupt

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_spurious_intr_vec_reg	; (esi) = APIC spurious interrupt vector reg (0FEE0_00F0H)
	mov	di,es:[esi]			; read current setting
	and	di,0ffh				; keep the vector field only
	shl	di,2				; 1 DWORD for each vector
	mov	eax,es:[di]			; (eax) = current vector
	mov	ds:apic_spurious_intr_save_area,di; save for later restore
	mov	ds:(apic_spurious_intr_save_area + 2),eax; save it for later restore
	mov	word ptr es:[di],(offset cgroup:dummy_apic_spurious_intr_handler - offset cgroup:smi_code_begin + orgbase)
	mov	es:[di+2],cs			; segment

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_task_priority_reg	; (esi) = APIC task priority reg (0FEE0_0080H)
	mov	eax,es:[esi]			; read current value of APIC task priority reg
	mov	ds:apic_task_priority_reg_save_area,eax; save it for later restore
	or	al,0ffh				; set priority to 15, so that APIC will not accept any interrupts
	jmp	short save_and_mask_apic_intr_10;

save_and_mask_apic_intr	endp

;---------------------------------------------------------------;
;		  RESTORE_AND_UNMASK_APIC_INTR			;
;---------------------------------------------------------------;
;	Input : (DS) PM BIOS data segment			;
;		STACK PRESENT					;
;	Output: NONE						;
;	Register destroyed : NONE				;
; NOTE :							;
;  * This will restore previously saved mask of all interrupts	;
;    generated thru local APIC of INTEL PENTIUM processor.	;
;  * (ES) has 4 GB limit at this point				;
;  * This routine should be used with BSP processor only	;
;---------------------------------------------------------------;

restore_and_unmask_apic_intr	proc	near

	push	es				;
	push	eax				;
	push	esi				;
	push	di				;

	push	0000h				;
	pop	es				; set (es) to 0000h to access 4 GB address space

	push	cx				;
	mov	cx,4				; restore 4 local interrupts
	mov	di,apic_lvt_timer_reg_save_area	; (di) = APIC local vector table for TIMER save area
restore_and_unmask_apic_intr_00:
	mov	esi,[di]			; (esi) = APIC reg address
	mov	eax,[di+4]			; (eax) = read saved data
	call	write_apic_reg			;
	add	edi,8				; point to next entry
	loop	restore_and_unmask_apic_intr_00	;
	pop	cx				;

	mov	di,ds:apic_spurious_intr_save_area; (di) = spurious interrupt vector restore pointer
	mov	eax,ds:(apic_spurious_intr_save_area + 2); data to restore
	mov	es:[di],eax			;

	call	get_local_apic_base_addr	; (esi) = local APIC base address
	or	si,apic_task_priority_reg	; (esi) = APIC task priority reg (0FEE0_0080H)
	mov	eax,ds:apic_task_priority_reg_save_area; get the saved value

;-----------------------------------------------;

save_and_mask_apic_intr_10::
	call	write_apic_reg			;

	pop	di				;
	pop	esi				;
	pop	eax				;
	pop	es				;

	ret

restore_and_unmask_apic_intr	endp

;---------------------------------------------------------------;
;		SAVE_MASK_APIC_LOCAL_VEC_TBL			;
;---------------------------------------------------------------;
;	Input : (ESI) APIC reg address				;
;		(DI) data save address				;
;		(ES) 0000h with 4GB limit			;
;	Output: NONE						;
;	Register destroyed : (EAX)				;
; NOTE :							;
;  * (ES) has 4 GB limit at this point				;
;---------------------------------------------------------------;

save_mask_apic_local_vec_tbl	proc	near

	mov	[di],esi			; save APIC reg address
	mov	eax,es:[esi]			; (eax) = read current value
	mov	[di+04],eax			; save the data
	or	eax,apic_intr_mask_bit		; mask local APIC interrupt

;---------------------------------------------------------------;
;			WRITE_APIC_REG				;
;---------------------------------------------------------------;
;	Input : (EAX) data to write				;
;		(ESI) APIC reg address				;
;		(ES) 0000h with 4GB limit			;
;	Output: NONE						;
;	Register destroyed : NONE				;
; NOTE :							;
;  * (ES) has 4 GB limit at this point				;
;---------------------------------------------------------------;

write_apic_reg	proc	near

	mov	es:[esi],eax			;
	mov	eax,es:[esi]			; read back to post write ???
	ret

write_apic_reg	endp
save_mask_apic_local_vec_tbl	endp

;---------------------------------------------------------------;
;		DUMMY_APIC_SPURIOUS_INTR_HANDLER		;
;---------------------------------------------------------------;
;	Input : NONE						;
;	Output: NONE						;
;	Register destroyed : NONE				;
;---------------------------------------------------------------;

dummy_apic_spurious_intr_handler	proc	far

	iret

dummy_apic_spurious_intr_handler	endp

;---------------------------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;**								**;
;**	(C)Copyright 1985-1996, American Megatrends Inc.	**;
;**								**;
;**			All Rights Reserved.			**;
;**								**;
;**		6145-F, Northbelt Parkway, Norcross,		**;
;**								**;
;**		Georgia - 30071, USA. Phone-(770)-246-8600.	**;
;**								**;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------------------------------;
;    POST TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;    POST TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;    POST TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;    POST TIME CORE BIOS DUAL/MULTIPROCESSOR SMI HANDLER CODE	;
;---------------------------------------------------------------;
;		SETUP_SMI_HANDLER_FOR_MULTIPLE_CPU		;
;---------------------------------------------------------------;
;	Input : (DS) SMRAM segment				;
;		(ES) SMRAM segment				;
;		(BL) bit 0 set for 32KB SMRAM			;
;		     bit 0 clear for 64KB or greater SMRAM	;
;		     bit 1 set for smbase requires relocation	;
;		     bit 1 clear for smbase relocation not reqd.;
;		     bit 3  bit 2				;
;		       0      0   ... INTEL type SMI		;
;		       0      1   ... CYRIX type SMI		;