api_reg.h

其乐达(Cheertek)LCD驱动芯片(CT675)的C51源代码

#ifndef _API_REG_H
#define _API_REG_H

// Device address
#define DEV_AD_ADDR             0x42
#define DEV_VD_ADDR             0x40
#define DEV_SC_ADDR             0xF4
#define DEV_TC_ADDR             0xF6

// ADC register table
#define REG_AD_Y_GAIN           0x03
#define REG_AD_Y_OFFSET         0x06
#define REG_AD_Y_BOFFSET        0x0E
#define REG_AD_SOG_THD          0x11
#define REG_AD_CLAMP_CTRL       0x12
#define REG_AD_XCLAMP_SEL       0x13
#define REG_AD_VTST_H           0x15
#define REG_AD_VINSEL           0x16
#define REG_AD_VTST_L           0x17
#define REG_AD_TEST             0x1A
#define REG_AD_SPEED            0x1B
#define REG_AD_TPAD             0x1C
#define REG_AD_YINSEL           0x20
#define REG_AD_CINSEL           0x23
#define REG_AD_PWDNB            0x25
#define REG_AD_C_BOFFSET        0x26
#define REG_AD_CSSEL            0x28

#define REG_AD_Y_MIDSHIFT       0x30
#define REG_AD_AB_RESULT        0x37
#define REG_AD_Y_HSCNT_VAL      0x38
#define REG_AD_Y_CKCNT_VAL      0x39
#define REG_AD_Y_CLAMP_OFF1     0x3A
#define REG_AD_Y_MID_VAL        0x3B
#define REG_AD_Y_CLAMP_OFF2     0x3C

#define REG_AD_AB_CTRL          0x50
#define REG_AD_C_HSCNT_VAL      0x58
#define REG_AD_C_CKCNT_VAL      0x59
#define REG_AD_C_CLAMP_OFF1     0x5A
#define REG_AD_C_MID_VAL        0x5B
#define REG_AD_C_CLAMP_OFF2     0x5C
#define REG_AD_CLAMPSEL_IS      0x5F

// Video Decoder register table
#define REG_VD_MISC_CTRL1       0x00
#define REG_VD_AUTO_MODE_1      0x01
#define REG_VD_AUTO_MODE_2      0x02
#define REG_VD_CORING_REG0      0x03
#define REG_VD_CHROMA0          0x04
#define REG_VD_DC_OFFSET        0x05
#define REG_VD_BRIGHT           0x06
#define REG_VD_CTRST            0x07
#define REG_VD_HUE              0x08
#define REG_VD_SAT              0x09
#define REG_VD_VSTART           0x0A
#define REG_VD_VWIDTH           0x0B
#define REG_VD_HSTART           0x0C
#define REG_VD_HWIDTH           0x0D
#define REG_VD_HS_START         0x0E
#define REG_VD_VCR_THD          0x0F

#define REG_VD_STATUS0          0x10
#define REG_VD_STATUS1          0x11
#define REG_VD_STATUS2          0x12
#define REG_VD_STATUS3          0x13
#define REG_VD_STATUS4          0x14
#define REG_VD_STATUS5          0x15
#define REG_VD_STATUS6          0x16
#define REG_VD_STATUS7          0x17
#define REG_VD_STATUS8          0x18
#define REG_VD_STATUS9          0x19
#define REG_VD_STATUS10         0x1A
#define REG_VD_STATUS11         0x1B
#define REG_VD_STATUS12         0x1C
#define REG_VD_STATUS13         0x1D
#define REG_VD_STATUS14         0x1E

// Scaler register table
#define REG_SC_VERSION          0x00
#define REG_SC_CLOCK_REG0       0x02
#define REG_SC_CLOCK_REG1       0x03
#define REG_SC_CLOCK_REG2       0x04
#define REG_SC_CLOCK_REG3       0x06
#define REG_SC_CLOCK_OFF        0x07
#define REG_SC_SOFT_RESET       0x08
#define REG_SC_MISC_CTRL1       0x0A
#define REG_SC_MISC_CTRL2       0x0B
#define REG_SC_HIV_CTRL         0x0C
#define REG_SC_SAR_CTRL         0x0E
#define REG_SC_SAR_DATA         0x0F

#define REG_SC_PPLL_CTRL0       0x20
#define REG_SC_PPLL_CTRL1       0x21
#define REG_SC_PPLL_CTRL2       0x22
#define REG_SC_VPLL_CTRL0       0x23
#define REG_SC_VPLL_CTRL1       0x24
#define REG_SC_VPLL_CTRL2       0x25
#define REG_SC_XPLL_CTRL0       0x26
#define REG_SC_XPLL_CTRL1       0x27
#define REG_SC_XPLL_CTRL2       0x28
#define REG_SC_CPH_CTRL0        0x29
#define REG_SC_CPH_CTRL1        0x2A
#define REG_SC_CPH_CTRL2        0x2B
#define REG_SC_CPH_CTRL3        0x2C
#define REG_SC_PRG_OUT          0x2D
#define REG_SC_MISC_PACK        0x2E

#define REG_SC_INPUT_CTRL0      0x01
#define REG_SC_OUT_CTRL2        0x05
#define REG_SC_MISC_CTRL0       0x09
#define REG_SC_STATUS           0x0D

#define REG_SC_IH_ASTART        0x10
#define REG_SC_IH_AWIDTH        0x12
#define REG_SC_IV_ASTART        0x14
#define REG_SC_IV_AWIDTH        0x16
#define REG_SC_IH_WRAP          0x18
#define REG_SC_VS_DELAY         0x1A
#define REG_SC_VS_SPDL          0x1B
#define REG_SC_VS_FPORCH        0x1C
#define REG_SC_IV_TOTAL         0x1E

#define REG_SC_PH_TOTAL         0x30
#define REG_SC_PH_ASTART        0x32
#define REG_SC_PH_AWIDTH        0x34
#define REG_SC_OFFSET_NO        0x36
#define REG_SC_PHS_PULWIDTH     0x37
#define REG_SC_PH_DELAY         0x38
#define REG_SC_PV_AWIDTH        0x3A
#define REG_SC_PV_TOTAL         0x3C
#define REG_SC_PVS_PULWIDTH     0x3E

#define REG_SC_BH_ASTART        0x40
#define REG_SC_BH_AEND          0x42
#define REG_SC_BV_AOFF_E        0x44
#define REG_SC_BV_AOFF_O        0x46
#define REG_SC_BV_ASTART        0x48
#define REG_SC_BV_AWIDTH        0x4A
#define REG_SC_FREEZE_HADDR     0x4C
#define REG_SC_FREEZE_VADDR     0x4E

#define REG_SC_SYNC_DIST        0x50
#define REG_SC_LHNV_DIST        0x52
#define REG_SC_LINE_MARGIN      0x54
#define REG_SC_LB_MARGIN        0x56
#define REG_SC_FREEZE_READ      0x58

#define REG_SC_VDX              0x60
#define REG_SC_VDY              0x61
#define REG_SC_VINC             0x62
#define REG_SC_SCALE_CTRL       0x63
#define REG_SC_HSD_HDX          0x64
#define REG_SC_HSD_HDY          0x65
#define REG_SC_HSD_HINC         0x66
#define REG_SC_ARX_INI          0x67
#define REG_SC_VDENO            0x68
#define REG_SC_VNEMU            0x69
#define REG_SC_IHSC_AWIDTH      0x6A

#define REG_SC_GCT_START        0x80
#define REG_SC_RED_GCT          0x81
#define REG_SC_GRN_GCT          0x82
#define REG_SC_BLUE_GCT         0x83
#define REG_SC_OSD_LUT          0x84
#define REG_SC_CLUT_ALPHA       0x85
#define REG_SC_OSDLUT_ADDR      0x86
#define REG_SC_FBKGND_RED       0x88
#define REG_SC_FBKGND_GRN       0x89
#define REG_SC_FBKGND_BLUE      0x8A

#define REG_SC_NR_CNTR1         0x90
#define REG_SC_NR_CNTR2         0x91
#define REG_SC_NRTHD_CONST      0x92
#define REG_SC_NEST_CONST       0x93
#define REG_SC_NRTHD_OFF        0x94
#define REG_SC_HP_CNTR          0x95
#define REG_SC_NE_THD           0x96
#define REG_SC_TASTE            0x98
#define REG_SC_YWUP_THD         0x99
#define REG_SC_YWDN_THD         0x9A
#define REG_SC_YBUP_THD         0x9B
#define REG_SC_YBDN_THD         0x9C
#define REG_SC_WBINV_THD        0x9D
#define REG_SC_COMPLX_THD1      0x9E
#define REG_SC_COMPLX_THD2      0x9F

#define REG_SC_YUV_CTRL         0xB0
#define REG_SC_Y_CNT_EDC_WT     0xB1
#define REG_SC_U_CNT_EDC_WT     0xB2
#define REG_SC_V_CNT_EDC_WT     0xB3
#define REG_SC_Y_PEAK_WT        0xB4
#define REG_SC_Y_CNTR_PK_WT     0xB5
#define REG_SC_U_PEAK_WT        0xB6
#define REG_SC_U_CNTR_PK_WT     0xB7
#define REG_SC_V_PEAK_WT        0xB8
#define REG_SC_V_CNTR_PK_WT     0xB9
#define REG_SC_Y_CNT_ED_COR     0xBA
#define REG_SC_U_CNT_ED_COR     0xBB
#define REG_SC_V_CNT_ED_COR     0xBC

#define REG_SC_SRGB_CTRL        0xE0
#define REG_SC_SRGB_YOFFSET     0xE1
#define REG_SC_SRGB_RCOEFF1     0xE2
#define REG_SC_SRGB_RCOEFF2     0xE4
#define REG_SC_SRGB_RCOEFF3     0xE6
#define REG_SC_SRGB_GCOEFF1     0xE8
#define REG_SC_SRGB_GCOEFF2     0xEA
#define REG_SC_SRGB_GCOEFF3     0xEC
#define REG_SC_SRGB_BCOEFF1     0xEE
#define REG_SC_SRGB_BCOEFF2     0xF0
#define REG_SC_SRGB_BCOEFF3     0xF2
#define REG_SC_SRGB_ROFFSET     0xF4
#define REG_SC_SRGB_GOFFSET     0xF5
#define REG_SC_SRGB_BOFFSET     0xF6

#define REG_SC_GRAPHIC_STA      0xC0
#define REG_SC_GRAPHIC_END      0xC1
#define REG_SC_FONT_ADDR        0xC2
#define REG_SC_FONT_LSB         0xC3
#define REG_SC_FONT_MSB         0xC4
#define REG_SC_FONT_AT          0xC5
#define REG_SC_FONT_DT          0xC6
#define REG_SC_OSD_AD0          0xC7
#define REG_SC_OSD_AD1          0xC8
#define REG_SC_OSD_AD2          0xC9
#define REG_SC_OSD_SYS_CTRL     0xCA
#define REG_SC_SPACECODE        0xCB
#define REG_SC_OSD_DIS_OPT1     0xCC
#define REG_SC_OSD_HPOS         0xCD
#define REG_SC_OSD_VPOS         0xCE
#define REG_SC_OSD_CTRL2        0xCF
#define REG_SC_OSD_CTRL         0xD0
#define REG_SC_OSD_DIS_OPT2     0xD1
#define REG_SC_OSDWIN_ADDR      0xD2
#define REG_SC_OSDWIN_DATA      0xD3

#define REG_SC_PWG1_INCTL       0xDA
#define REG_SC_PWG2_INCTL       0xDB
#define REG_SC_PWG3_INCTL       0xDC
#define REG_SC_PWG1_OUTCTL      0xDD
#define REG_SC_PWG2_OUTCTL      0xDE
#define REG_SC_PWG3_OUTCTL      0xDF

#define REG_SC_ICLK_MEASURE     0xD6
#define REG_SC_PCLK_MEASURE     0xD8
#define REG_SC_PWM_CTRL         0xF9
#define REG_SC_PWM3_DUTY        0xFA
#define REG_SC_PWM2_DUTY        0xFB
#define REG_SC_PWM1_DUTY        0xFC
#define REG_SC_PWM1_PERIOD      0xFE

#endif // _API_REG_H