s1d13506.c

Project with S1D13506 and AVR M8515

#include <avr/io.h>
#include "portbits.h"
#include "global.h"
#include "s1d13506.h"
#include "grafik.h"

#define F_CPU         16000000 
#include <util/delay.h>

/* DRAM Memory usage:

           ___________________
 0x000000 |                   |
          |                   |
          |                   |
          |                   |
          |  CRT/TV Picture   | 1024kByte
          |                   |
          |                   |
          |                   |
          |___________________|
 0x100000 |                   |
          |                   |
          |                   |
          |                   |
          |  LCD/TFT Picture  | 640kByte
          |                   |
          |                   |
          |                   |
          |___________________|
 0x1A0000 |                   |
          |  CRT Ink/Cursor   | 128kByte
          |___________________|
 0x1C0000 |                   |
          |  LCD Ink/Cursor   | 128kByte
          |___________________|
 0x1E0000 |                   |
          | Dual Panel Buffer | 128kByte
 0x200000 |___________________|

*/


volatile unsigned char *const mem=(unsigned char *const)1024;

void s1d13506_init(void)
{
	MCUCR=(1<<SRE);
	EMCUCR=(1<<SRW11);
	SFIOR=(1<<XMM0)|(1<<XMM1)|(1<<XMM2);	//256Byte IO

	RESET=0;				//Reset\ Low
	_delay_ms(1);
	RESET=1;				//Reset\ High

	_delay_ms(10);

	s1d13506_writereg(0x01,0x00);	// enable interface

	s1d13506_writereg(0x1F0,0x00);	// power save mode off
	s1d13506_writereg(0x04,0x0E);	// GPIO: output
	s1d13506_writereg(0x10,0x00);	// DRAM clk: CLKI
	s1d13506_writereg(0x14,0x32);	// Pixel clock: 17,7MHz/4
	s1d13506_writereg(0x18,0xA0);	// CRT/TV clock: 33,3MHz*2/3
	s1d13506_writereg(0x1C,0x00);	// Media Plug Clock
	s1d13506_writereg(0x1E,0x00);	// MCLK<->BLCK: asynchronous
	s1d13506_writereg(0x20,0x00);	// EDO DRAM, 2 CAS
	s1d13506_writereg(0x21,0x05);	// CBR DRAM refresh, every 16ms
	s1d13506_writereg(0x20,0x00);	// optimize EDO DRAM timing
	s1d13506_writereg(0x21,0x00);	// optimize EDO DRAM timing
	s1d13506_writereg(0x1F4,0x00);	// watchdog off
	s1d13506_writereg(0x1FC,0x00);	// all displays off

	s1d13506_writereg(0x30,0x12);	// LCD: 640x480, dualscan
	s1d13506_writereg(0x31,0x00);	// LCD: n-line: 0
	s1d13506_writereg(0x32,0x52);	// LCD: XSize: 640 Pixel
	s1d13506_writereg(0x34,0x03);	// LCD: non displayed: 32 Pixel
	s1d13506_writereg(0x35,0x00);	// LCD: start pos
	s1d13506_writereg(0x36,0x00);	// LCD: FPLINE: active high
	s1d13506_writereg(0x38,0xDF);	// LCD: Ysize: 480
	s1d13506_writereg(0x39,0x01);	// LCD: Ysize: 480
	s1d13506_writereg(0x3A,0x01);	// LCD: non displayed: 2
	s1d13506_writereg(0x3B,0x00);	// LCD: start pos
	s1d13506_writereg(0x3C,0x00);	// LCD: FPFRAME: active high
	s1d13506_writereg(0x40,0x03);	// LCD: 8bpp
	s1d13506_writereg(0x41,0x00);	// LCD: dual buffer and dithering enabled
	s1d13506_writereg(0x42,0x00);	// LCD: startadress: 0x100000
	s1d13506_writereg(0x43,0x00);	// LCD: startadress: 0x100000
	s1d13506_writereg(0x44,0x10);	// LCD: startadress: 0x100000
	s1d13506_writereg(0x46,0x80);	// LCD: adress offset: 640
	s1d13506_writereg(0x47,0x02);	// LCD: adress offset: 640
	s1d13506_writereg(0x48,0x00);	// LCD: panning: 0
	s1d13506_writereg(0x4A,0x00);	// LCD: FIFO threshold: automatic
	s1d13506_writereg(0x4B,0x00);	// LCD: FIFO threshold: automatic

	s1d13506_writereg(0x50,0x41);	// CRT: Xsize: 528
	s1d13506_writereg(0x52,0x11);	// CRT: non display: 144
	s1d13506_writereg(0x53,0x05);	// CRT: start pos: 43 pixel
	s1d13506_writereg(0x54,0x03);	// CRT: HSync: active low, 32pixel
	s1d13506_writereg(0x56,0xDF);	// CRT: Ysize: 480
	s1d13506_writereg(0x57,0x01);	// CRT: Ysize: 480
	s1d13506_writereg(0x58,0x1F);	// CRT: non displayed: 32
	s1d13506_writereg(0x59,0x0B);	// CRT: start pos: 12
	s1d13506_writereg(0x5A,0x07);	// CRT: VSync: active low, 8 lines
	s1d13506_writereg(0x5B,0x01);	// CRT: TV mode: PAL
	s1d13506_writereg(0x60,0x03);	// CRT: 8bpp
	s1d13506_writereg(0x62,0x00);	// CRT: startadress: 0x000000
	s1d13506_writereg(0x63,0x00);	// CRT: startadress: 0x000000
	s1d13506_writereg(0x64,0x00);	// CRT: startadress: 0x000000
	s1d13506_writereg(0x66,0x08);	// CRT: adress offset: 528
	s1d13506_writereg(0x67,0x01);	// CRT: adress offset: 528
	s1d13506_writereg(0x68,0x00);	// CRT: panning: 0
	s1d13506_writereg(0x6A,0x00);	// CRT: FIFO threshold: automatic
	s1d13506_writereg(0x6B,0x00);	// CRT: FIFO threshold: automatic

	s1d13506_writereg(0x70,0x00);	// LCD: Ink/Cursor: inactive
	s1d13506_writereg(0x71,0xD0);	// LCD: Ink/Cursor adress: 0x1A0000
	s1d13506_writereg(0x72,0x00);	// LCD: Ink/Cursor pos x: 0
	s1d13506_writereg(0x73,0x00);	// LCD: Ink/Cursor pos x: 0
	s1d13506_writereg(0x74,0x00);	// LCD: Ink/Cursor pos y: 0
	s1d13506_writereg(0x75,0x00);	// LCD: Ink/Cursor pos y: 0
	s1d13506_writereg(0x76,0x00);	// LCD: Ink/Cursor blue0: 0
	s1d13506_writereg(0x77,0x00);	// LCD: Ink/Cursor green0: 0
	s1d13506_writereg(0x78,0x00);	// LCD: Ink/Cursor red0: 0
	s1d13506_writereg(0x7A,0x00);	// LCD: Ink/Cursor blue1: 0
	s1d13506_writereg(0x7B,0x00);	// LCD: Ink/Cursor green1: 0
	s1d13506_writereg(0x7C,0x00);	// LCD: Ink/Cursor red1: 0
	s1d13506_writereg(0x7E,0x00);	// LCD: Ink/Cursor FIFO: automatic

	s1d13506_writereg(0x80,0x00);	// CRT: Ink/Cursor: inactive
	s1d13506_writereg(0x81,0xE0);	// CRT: Ink/Cursor adress: 0x1C0000
	s1d13506_writereg(0x82,0x00);	// CRT: Ink/Cursor pos x: 0
	s1d13506_writereg(0x83,0x00);	// CRT: Ink/Cursor pos x: 0
	s1d13506_writereg(0x84,0x00);	// CRT: Ink/Cursor pos y: 0
	s1d13506_writereg(0x85,0x00);	// CRT: Ink/Cursor pos y: 0
	s1d13506_writereg(0x86,0x00);	// CRT: Ink/Cursor blue0: 0
	s1d13506_writereg(0x87,0x00);	// CRT: Ink/Cursor green0: 0
	s1d13506_writereg(0x88,0x00);	// CRT: Ink/Cursor red0: 0
	s1d13506_writereg(0x8A,0x00);	// CRT: Ink/Cursor blue1: 0
	s1d13506_writereg(0x8B,0x00);	// CRT: Ink/Cursor green1: 0
	s1d13506_writereg(0x8C,0x00);	// CRT: Ink/Cursor red1: 0
	s1d13506_writereg(0x8E,0x00);	// CRT: Ink/Cursor FIFO: automatic

	s1d13506_writereg(0x1E0,0x00);	// LUT: select LCD&CRT LUT
	unsigned short i;
	for (i=0; i<256; i++)
		s1d13506_writepal(i,(i&7)*32,((i/8)&7)*32,(i/64)*64);

	s1d13506_writereg(0x1FC,0x02);	// CRT on

	x_size=528;
	y_size=480;
}

void s1d13506_writepal(unsigned char i, unsigned char r, unsigned char g, unsigned char b)
{
	MR=0;
	CS=0;
	ADRX=0;
	ADRH=1;
	mem[0xE2] = i;
	mem[0xE4] = r&0xF0;
	mem[0xE4] = g&0xF0;
	mem[0xE4] = b&0xF0;
	CS=1;
}

void s1d13506_readpal(unsigned char i, unsigned char *r, unsigned char *g, unsigned char *b)
{
	MR=0;
	CS=0;
	ADRX=0;
	ADRH=1;
	mem[0xE2] = i;
	*r = mem[0xE4]&0xF0;
	*g = mem[0xE4]&0xF0;
	*b = mem[0xE4]&0xF0;
	CS=1;
}

void s1d13506_writereg(unsigned short reg, unsigned char wert)
{	CONVERTW adr;
	adr.w=reg;
	CS=0;
	MR=0;
	ADRX=0;
	ADRH=adr.b[1];
	CS=0;
	mem[adr.b[0]]=wert;
	CS=1;
}

unsigned char s1d13506_readreg(unsigned short reg)
{	CONVERTW adr;
	unsigned char val;
	adr.w=reg;
	CS=0;
	MR=0;
	ADRX=0;
	ADRH=adr.b[1];
	CS=0;
	val=mem[adr.b[0]];
	CS=1;
	return val;
}

void s1d13506_writemem(unsigned long adress, unsigned char wert)
{	CONVERTDW adr;
	adr.dw=adress;
	CS=0;
	MR=1;
	ADRX=adr.b[2];
	ADRH=adr.b[1];
	CS=0;
	mem[adr.b[0]]=wert;
	CS=1;
}

unsigned char s1d13506_readmem(unsigned long adress)
{	CONVERTDW adr;
	unsigned char val;
	adr.dw=adress;
	CS=0;
	MR=1;
	ADRX=adr.b[2];
	ADRH=adr.b[1];
	CS=0;
	val=mem[adr.b[0]];
	CS=1;
	return val;
}