option.h

44b0x ucos 原版官方移植程序S3C3410X-ucos-ii.zip

/**********************************************************************/
/*		Header file for k401lib.c and 401mon.c		      */
/**********************************************************************/
/*	Modified and programmed by Yong-Hyeon Kim		      */
/*	Description : 1999. 12. 20 first edited			      */
/*		      2000. 06. 09 added define for each bloak	      */
/**********************************************************************/

/* System Configuration */
#define _RAM_STARTADDRESS	0x1000000
#define _ISR_STARTADDRESS       0x17fff00
#define _CPU_ASICBASE           0x7ff0000

// Memory Type Setting
// BUSWIDTH : 8, 16
// DRAM TYPE : "DRAM", "SDRAM"
#define BUSWIDTH	(16)
#define DRAMTYPE	(SDRAM)

/* Oerating Frequency */
#define MCLK		(40000000)

/***********************************************************************
 *	System Register Address Configuration Register Definitions
 *
 *	 21   20 19   18  17 16   15 14            4  3   2   1   0
 *	+-------+-------+---+-------+---------------+---+---+---+---+
 *	|  MT1  |  MT0  |AME|  CM   |     SFRSA     | X | WE| CE| ST|
 *	+-------+-------+---+-------+---------------+---+---+---+---+
 *
 *	MT1: Memory type of bank7	00: ROM/SRAM, 01: FP, 10: EDO, 11: SDRAM
 *	MT0: Memory type of bank6	00: ROM/SRAM, 01: FP, 10: EDO, 11: SDRAM
 *	AME: Address Mux enable		0: disable, 1:enable
 *	CM: Cache mode (Cache size)	00: 2KB cache, 01: 4KB cache, 10: 0KB cache
 *					    2KB SRAM,      0KB SRAM       4KB SRAM
 *	SFRSA: SFR Start Address	Start Address=(SFRSA<<16)
 *	WE: Write Buffer enable		0: disable, 1: enable
 *	CE: Cache enable		0: disable, 1: enable
 *	ST: Stall enable		0: disable, 1: enable
 **********************************************************************/
/* SYSCFG[0] */
#define STALL_ON	(0x1<<0)
#define STALL_OFF	(0x0<<0)

/* SYSCFG[1] */
#define CACHE_ON	(0x1<<1)
#define CACHE_OFF	(0x0<<1)

/* SYSCFG[2] */
#define WRBUF_ON	(0x1<<2)
#define WRBUF_OFF	(0x0<<2)

/* SYSCFG[14:4] */
#define SFR_STARTADDRESS (0x7ff<<4)

/* SYSCFG[16:15] */
#define SYSCFG_0KB (0x2<<15)
#define SYSCFG_2KB (0x0<<15)
#define SYSCFG_4KB (0x1<<15)

/* SYSCFG[17] */
#define ADDRESS_MUX_ON	(0x1<<17)
#define ADDRESS_MUX_OFF	(0x0<<17)

/* SYSCFG[19:18] */
#define MEMORY0_ROM	(0x0<<18)
#define MEMORY0_FP	(0x1<<18)
#define MEMORY0_EDO	(0x2<<18)
#define MEMORY0_SDRAM	(0x3<<18)

/* SYSCFG[21:20] */
#define MEMORY1_ROM	(0x0<<20)
#define MEMORY1_FP	(0x1<<20)
#define MEMORY1_EDO	(0x2<<20)
#define MEMORY1_SDRAM	(0x3<<20)

/**********************************************************************
 *	Basic Timer Control Register Definition
 *
 *	 15                            8 7             4 3    2  1   0
 *	+-------------------------------+---------------+------+---+---+
 *	|             WDTE              |       X       |  CS  |BTC|WDC|
 *	+-------------------------------+---------------+------+---+---+
 *
 *	WDTE: Watchdog Timer enable	10100101: enable, other: disable
 *	CS: Clock source		00: Fin/2^13, 01: Fin/2^12, 10: Fin/2^11, 11: Fin/2^9
 *	BTC: Basic Timer clear		0: Not clear, 1: Clear
 *	WDC: Watch-dog Timer clear	0: Not clear, 1: Clear
 **********************************************************************/
/* BTCON[0] */
#define WDT_CLEAR	(0x1)
#define WDT_DONT_CLEAR	(0x0)

/* BTCON[1] */
#define BT_CLEAR	(0x2)
#define BT_DONT_CLEAR	(0x0)

/* BTCON[3:2] */
#define CS_2_13		(0x0<<2)
#define CS_2_12		(0x1<<2)
#define CS_2_11		(0x2<<2)
#define CS_2_9		(0x3<<2)

/* BTCON[15:8] */
#define WDT_ENABLE	(0x0<<8)
#define WDT_DISABLE	(0xa5<<8)

/**********************************************************************
 *	UART Line Control Register Definitions
 *
 *	  7   6   5       3   2   1   0
 *	+---+---+-----------+---+---+---+
 *	| X |IRM|Parity Mode| SB|  WL   |
 *	+---+---+-----------+---+-------+
 *
 *	WL: Word Length			00: 5 bits, 01: 6 bits, 10: 7 bits, 11: 8 bits
 *	SB: Number of Stop bit		0: 1 bit per frame, 1: 2 bits per frame
 *	Parity Mode:			0xx: No parity, 100: Odd parity, 101: Even parity
 *					110: Parity forced/checked as "1"
 *					111: Parity forced/checked as "0"
 *	IRM: Infra-red enable		0: Normal mode, 1: IrDA mode
 **********************************************************************/
#define UART_MODE_WORD_5	(0x00)
#define UART_MODE_WORD_6	(0x01)
#define UART_MODE_WORD_7	(0x02)
#define UART_MODE_WORD_8	(0x03)

#define UART_MODE_STOP_1	(0x00)
#define UART_MODE_STOP_2	(0x04)

#define UART_MODE_PARITY_NONE	(0x00)
#define UART_MODE_PARITY_ODD	(0x20)
#define UART_MODE_PARITY_EVEN	(0x28)

#define UART_MODE_IRDA_OFF	(0x00)
#define UART_MODE_IRDA_ON	(0x40)

#define UART_MODE_DEFAULT	(UART_MODE_IRDA_OFF | \
				 UART_MODE_PARITY_NONE | \
				 UART_MODE_STOP_1 | \
				 UART_MODE_WORD_8)

/**********************************************************************
 *	UART Control Register Definitions
 *
 *	  7   6   5   4   3   2   1   0
 *	+---+---+---+---+-------+-------+
 *	|RTO|RSI|LBM|SBS|  TxM  |  RxM  |
 *	+---+---+---+---+-------+-------+
 *
 *	RxM: Receive mode		00: disable, 01: Interrupt, 10: DMA0, 11: DMA1
 *	TxM: Transmit mode		00: disable, 01: Interrupt, 10: DMA0, 11: DMA1
 *	SBS: Send Break			0: No break, 1: Send break
 *	LBM: Loop-Back mode		0: Normal, 1: Loop-back
 *	RSI: Rx status interrupt enable	0: disable, 1: enable
 *	RTO: Rx time out enable		0: disable, 1: enable
 **********************************************************************/

#define UART_CTRL_RCV_MODE_INT		(0x1)
#define UART_CTRL_RCV_MODE_DMA0		(0x2)
#define UART_CTRL_RCV_MODE_DMA1		(0x3)

#define UART_CTRL_XMT_MODE_INT		(0x1<<2)
#define UART_CTRL_XMT_MODE_DMA0		(0x2<<2)
#define UART_CTRL_XMT_MODE_DMA1		(0x3<<2)

#define UART_CTRL_DONT_SEND_BREAK	(0x00)
#define UART_CTRL_SEND_BREAK		(0x10)

#define UART_CTRL_NO_LOOPBACK		(0x00)
#define UART_CTRL_LOOPBACK		(0x20)

#define UART_CTRL_RCV_STATUS_INT_OFF	(0x00)
#define UART_CTRL_RCV_STATUS_INT_ON	(0x40)

#define UART_CTRL_RCV_TIMEOUT_OFF	(0x00)
#define UART_CTRL_RCV_TIMEOUT_ON	(0x80)

#define UART_CTRL_DEFAULT		(UART_CTRL_RCV_MODE_INT | \
					 UART_CTRL_XMT_MODE_INT | \
					 UART_CTRL_DONT_SEND_BREAK | \
					 UART_CTRL_NO_LOOPBACK | \
					 UART_CTRL_RCV_STATUS_INT_ON | \
					 UART_CTRL_RCV_TIMEOUT_OFF)

/**********************************************************************
 *	UART Status Register Definitions
 *
 *	  7   6   5   4   3   2   1   0
 *	+---+---+---+---+---+---+---+---+
 *	|   |   |   |   |   |   |   |   |
 *	+---+---+---+---+---+---+---+---+
 *
 *	Bit 0: Overrun error		0: no error, 1: overrun
 *	Bit 1: Parity error		0: no error, 1: parity error
 *	Bit 2: Frame error		0: no error, 1: frame error
 *	Bit 3: Break intr occurred	0: no break, 1: break rcved
 *	Bit 4: Receive time out		0: no receive time out, 1: receive time out
 *	Bit 5: Data Rcv			0: no data,  1: data rcved.
 *	Bit 6: Xmit holding reg. empty	0: ....	     1: Empty
 *	Bit 7: Transmitter empty	0: Tx in progress, 1: empty
 **********************************************************************/
#define UART_STAT_OVERRUN		(0x01)
#define UART_STAT_PARITY		(0x02)
#define	UART_STAT_FRAME			(0x04)
#define	UART_STAT_BREAK			(0x08)
#define UART_STAT_RCV_TIMEOUT		(0x10)
#define UART_STAT_RCV_DATA		(0x20)
#define	UART_STAT_XMT_HOLDING_EMPTY	(0x40)
#define	UART_STAT_XMT_SHIFT_EMPTY	(0x80)

#define	UART_STAT_ERROR	    		(UART_STAT_OVERRUN | UART_STAT_PARITY | UART_STAT_FRAME)