sc6600d_reg.h

展讯SC6600D例程

#define EXT_MEM_CTL_BEGIN       		0x20000000      //External Memory Control registers.
#define EXT_MEM_CTL_END         		0x2FFFFFFF
                                		
#define PERIPHERAL_ADD_BEGIN    		0x80000000      //Peripheral Address Space.
#define PERIPHERAL_ADD_END      		0xBFFFFFFF
                                		
#define ARM_TEST_ADD_BEGIN      		0xC0000000      //ARM Test.
#define ARM_TEST_ADD_END        		0xDFFFFFFF

//External Memory (8 CHIP Select).
#define EXTM_XCSN0_START        		0x00000000
#define EXTM_XCSN0_END          		0x03FFFFFF
#define EXTM_XCSN1_START        		0x04000000
#define EXTM_XCSN1_END          		0x07FFFFFF
                                		
#define EXTM_XCSN2_START        		0x08000000
#define EXTM_XCSN2_END          		0x0BFFFFFF
#define EXTM_XCSN3_START        		0x0C000000
#define EXTM_XCSN3_END          		0x0FFFFFFF
                                		
#define EXTM_XSCN4_START        		0x50000000
#define EXTM_XSCN4_END          		0x53FFFFFF
#define EXTM_XSCN5_START        		0x54000000
#define EXTM_XSCN5_END          		0x57FFFFFF
#define EXTM_XSCN6_START        		0x58000000
#define EXTM_XSCN6_END          		0x5BFFFFFF
#define EXTM_XSCN7_START        		0x5C000000
#define EXTM_XSCN7_END          		0x5FFFFFFF

/*----------external memory cotnrol registers----------*/
#define EXT_MEM_CTL_BASE        		0x20000000
#define EXT_MEM_CTL0            		(EXT_MEM_CTL_BASE + 0x0000)
#define EXT_MEM_CTL1            		(EXT_MEM_CTL_BASE + 0x0004)
#define EXT_MEM_CTL2            		(EXT_MEM_CTL_BASE + 0x0008)
#define EXT_MEM_CTL3            		(EXT_MEM_CTL_BASE + 0x000C)
#define EXT_MEM_CTL4            		(EXT_MEM_CTL_BASE + 0x0010)
#define EXT_MEM_CTL5            		(EXT_MEM_CTL_BASE + 0x0014)
#define EXT_MEM_CTL6            		(EXT_MEM_CTL_BASE + 0x0018)
#define EXT_MEM_CTL7            		(EXT_MEM_CTL_BASE + 0x001C)
#define EXT_MEM_INI             		(EXT_MEM_CTL_BASE + 0x0020)
#define EXT_MEM_MSCTL           		(EXT_MEM_CTL_BASE + 0x0024)

#define ARM_INTERNAL_MEM_START  		0x40008000
#define ARM_INTERNAL_MEM_END    		0x4000FFFF

/*----------Internal On Chip Memory----------*/
#define IOCM0_START             		0x40000000
#define IOCM0_END               		0x40003FFF
#define IOCM1_START             		0x40004000
#define IOCM1_END               		0x40007FFF
#define IOCM2_START             		0x40008000
#define IOCM2_END               		0x4000BFFF
#define IOCM3_START             		0x4000C000
#define IOCM3_END               		0x4000FFFF

//the extenal memory control register setting under different frequency
#define MCU13M_ECS0_VALUE       		0x08020008
#define MCU13M_ECS1_VALUE       		0x08020008

#define MCU26M_ECS0_VALUE       		0x08021108
#define MCU26M_ECS1_VALUE       		0x08021108

#define MCU39M_ECS0_VALUE       		0x08021208
#define MCU39M_ECS1_VALUE       		0x08021208

#define MCU52M_ECS0_VALUE       		0x08022308
#define MCU52M_ECS1_VALUE       		0x08022308

#define MCU71M_ECS0_VALUE       		0x08024508
#define MCU71M_ECS1_VALUE       		0x08024508

#define MCU78M_ECS0_VALUE       		0x08024508
#define MCU78M_ECS1_VALUE       		0x08024508

#define MCU104M_ECS0_VALUE       		0x08026708
#define MCU104M_ECS1_VALUE       		0x08026708

#define MCU_MAX_ECS0_VALUE      		MCU104M_ECS0_VALUE
#define MCU_MAX_ECS1_VALUE      		MCU104M_ECS1_VALUE

#define DEFAULT_ECS_VALUE				0x0803eeef
#define	ECS_MAX_SUPPORT_NUMBER			8

#define DEFAULT_INT_MEM_CTL     		0xF             	//ARM only use 0x4000_8000 - 0x4000_FFFF

/*----------bus monitor control registers----------*/
#define BUS_MON_CTL_BASE        		0x20000028     //to be added later


/*----------DMA Ctronl Registers----------*/
#define DMA_CTL_BASE            		0x20100000
#define DMA_GEN                 		(DMA_CTL_BASE + 0x0000)
#define DMA_CHN_IE              		(DMA_CTL_BASE + 0x0004)
#define DMA_CHN0_BASE           		(DMA_CTL_BASE + 0x0020)
#define DMA_CHN1_BASE           		(DMA_CTL_BASE + 0x0040)
#define DMA_CHN2_BASE           		(DMA_CTL_BASE + 0x0060)
#define DMA_CHN3_BASE           		(DMA_CTL_BASE + 0x0080)
#define DMA_CHN4_BASE           		(DMA_CTL_BASE + 0x00A0)
#define DMA_CHN5_BASE           		(DMA_CTL_BASE + 0x00C0)
#define DMA_CHN6_BASE           		(DMA_CTL_BASE + 0x00E0)
#define DMA_CHN7_BASE           		(DMA_CTL_BASE + 0x0100)

/*----------Peripheral Address Space----------*/
#define INT_CTL_BASE            		0x80000000
#define TIMER_CTL_BASE          		0x81000000
#define STOP_REMAP_CTL_BASE     		0x82000000
#define ARM_VBC_BASE     				0x82003000
#define ARM_UART0_BASE          		0x83000000
#define ARM_UART1_BASE          		0x84000000
#define SIM_BASE                		0x85000000
#define I2C_BASE                		0x86000000
#define KPD_BASE                		0x87000000
#define PWM_BASE                		0x88000000
#define RTC_BASE                		0x89000000
#define WDG_BASE                		0x89003000
#define GPIO_BASE               		0x8A000000
#define GREG_BASE               		0x8B000000
#define PIN_CTL_BASE            		0x8C000000
#define GEA_BASE                		0x8D000000
#define ARM_UART2_BASE          		0x8E000000
#define PCM_BASE                		0x8F000000
                                		

/*----------Interrupt Control Registers----------*/
//INT_CTL_BASE          0x80000000
#define INT_IRQ_BASE            		(INT_CTL_BASE + 0x0000)
#define INT_IRQ_STS             		(INT_CTL_BASE + 0x0000) //Interrupt status after masked by irq_enable.
#define INT_IRQ_RAW_STS         		(INT_CTL_BASE + 0x0004) //Interrupt status from different interrupt source.
#define INT_IRQ_EN              		(INT_CTL_BASE + 0x0008) //Enable bits  for the corresponding interrupt sources. 
#define INT_IRQ_DISABLE         		(INT_CTL_BASE + 0x000C) 
#define INT_IRQ_SOFT            		(INT_CTL_BASE + 0x0010)
#define INT_IRQ_TEST_SRC				(INT_CTL_BASE + 0x0014)
#define INT_IRQ_TEST_SEL				(INT_CTL_BASE + 0x0018)
#define INT_IRQ_UINT_STS        		(INT_CTL_BASE + 0x001C)
#define INT_FIQ_STS             		(INT_CTL_BASE + 0x0020)
#define INT_FIQ_RAW_STS         		(INT_CTL_BASE + 0x0024)
#define INT_FIQ_EN              		(INT_CTL_BASE + 0x0028)
#define INT_FIQ_DISABLE         		(INT_CTL_BASE + 0x002C)
#define INT_FIQ_SOFT            		(INT_CTL_BASE + 0x0030)
#define INT_FIQ_TEST_SRC				(INT_CTL_BASE + 0x0034)
#define INT_FIQ_TEST_SEL				(INT_CTL_BASE + 0x0038)
#define INT_UINT_CTL					(INT_CTL_BASE + 0x003C)

/*----------Timer Control Register----------*/
//TIMER_CTL_BASE        0x81000000
#define TIMER0_BASE             		(TIMER_CTL_BASE + 0x0000)
#define TM0_LOAD                		(TIMER0_BASE + 0x0000)          //Write to this register will reload the timer with the new value.
#define TM0_VALUE               		(TIMER0_BASE + 0x0004)          //Return the current timer value.
#define TM0_CTL                 		(TIMER0_BASE + 0x0008)
#define TM0_CLR                 		(TIMER0_BASE + 0x000C)          //Write to this register will clear the interrupt generated by this timer.
                                		
#define TIMER1_BASE             		(TIMER_CTL_BASE + 0x0020)
#define TM1_LOAD                		(TIMER1_BASE + 0x0000)          //Write to this register will reload the timer with the new value.
#define TM1_VALUE               		(TIMER1_BASE + 0x0004)          //Return the current timer value.
#define TM1_CTL                 		(TIMER1_BASE + 0x0008)  
#define TM1_CLR                 		(TIMER1_BASE + 0x000C)          //Write to this register will clear the interrupt generated by this timer.


/*----------Pause Control Register----------*/
//PAUSE_CTL_BASE                0x82000000
#define PAUSE_CTL_EN            		(PAUSE_CTL_BASE + 0x0000)       //Write to this register will pause the mcu
#define PAUSE_REMAP_CTL         		(PAUSE_CTL_BASE + 0x0020)

//-----------------------------------------------
//UART0, UART1 Registers
//ARM_UART0_BASE        				0x83000000
//ARM_UART1_BASE        				0x84000000
#define ARM_UART_TXD            		0x0000  //Write data to this address initiates a character transmission through tx fifo.
#define ARM_UART_RXD            		0x0004  //Reading this register retrieves the next data byte from the rx fifo.
#define ARM_UART_STS0           		0x0008
#define ARM_UART_STS1           		0x000C
#define ARM_UART_IEN            		0x0010
#define ARM_UART_ICLR           		0x0014
#define ARM_UART_CTL0           		0x0018
#define ARM_UART_CTL1           		0x001C
#define ARM_UART_CTL2           		0x0020
#define ARM_UART_CLKD0          		0x0024
#define ARM_UART_CLKD1          		0x0028
#define ARM_UART_STS2           		0x002C
                                		
#define DSP_UART1_Base          		0xBE00
#define DSP_UART2_Base          		0xBF00
#define DSP_UART_TXD            		0xBE00  //Write data to this address initiates a character transmission through tx fifo.
#define DSP_UART_RXD            		0xBE01  //Reading this register retrieves the next data byte from the rx fifo.
#define DSP_UART_STS0           		0xBE02
#define DSP_UART_STS1           		0xBE03
#define DSP_UART_IEN            		0xBE04
#define DSP_UART_ICLR           		0xBE05
#define DSP_UART_CTL0           		0xBE06
#define DSP_UART_CTL1           		0xBE07
#define DSP_UART_CTL2           		0xBE08
#define DSP_UART_CLKD0          		0xBE09
#define DSP_UART_CLKD1          		0xBE0A
#define DSP_UART_STS2           		0xBE0B


/*----------SIM Control Regosters----------*/
//SIM_BASE      0x85000000
#define SIM_TX                  		(SIM_BASE + 0x0000)     //Writing to this reg will send data to tx fifo and then the data get transmitted.
#define SIM_RX                  		(SIM_BASE + 0x0004)     //Read from this address retrieve data from rx fifo.
#define SIM_STS0                		(SIM_BASE + 0x0008)     //Status.
#define SIM_STS1                		(SIM_BASE + 0x000C)     //Status.
#define SIM_IE                  		(SIM_BASE + 0x0010)     //Interrupt Enable.
#define SIM_ICLR                		(SIM_BASE + 0x0014)     //Interrupt clear.
#define SIM_CTL0                		(SIM_BASE + 0x0018)		//Contorl 0 register
#define SIM_CTL1                		(SIM_BASE + 0x001C)		//Control 1 register
#define SIM_RX_CK_DVD           		(SIM_BASE + 0x0020)		//the SIM clock divider to interpret the SIM data
#define SIM_SHE                 		(SIM_BASE + 0x0024)		
#define SIM_TGC                 		(SIM_BASE + 0x0028)
#define SIM_WDT                 		(SIM_BASE + 0x002C)
#define SIM_INT_M               		(SIM_BASE + 0x0030)
#define SIM_TX_CK_DVD           		(SIM_BASE + 0x0034)
#define SIM_WDT1                		(SIM_BASE + 0x0038)

/*----------I2C Register----------*/
//I2C_BASE      0x86000000
#define I2C_CTL                 		(I2C_BASE + 0x0000)
#define I2C_CMD                 		(I2C_BASE + 0x0004)
#define I2C_CLKD0               		(I2C_BASE + 0x0008)
#define I2C_CLKD1               		(I2C_BASE + 0x000C)
#define I2C_RST                 		(I2C_BASE + 0x0010)
#define I2C_CMD_BUF             		(I2C_BASE + 0x0014)

/*----------Keypad Register----------*/
//KPD_BASE      0x87000000
#define KPD_STS                 		(KPD_BASE + 0x0000)
#define KPD_CTL                 		(KPD_BASE + 0x0004)
#define KPD_ICLR                		(KPD_BASE + 0x0008)
#define KPD_POLARITY            		(KPD_BASE + 0x000C)
#define KPD_CLK0                		(KPD_BASE + 0x0010)
#define KPD_CLK1                		(KPD_BASE + 0x0014)
#define KPD_INT_MSK             		(KPD_BASE + 0x0018)
#define KPD_PBINT_CTL           		(KPD_BASE + 0x0028)
#define KPD_PBINT_CNT           		(KPD_BASE + 0x002C)
#define KPD_PBINT_CNT_REG       		(KPD_BASE + 0x0030)

/*----------System Count----------*/
#define SYS_CNT0						(KPD_BASE + 0x001C)
#define SYS_CTL	                		(KPD_BASE + 0x0024)

/*----------PWM Register----------*/
//PWM_BASE      0x88000000
#define PWM0_PRESCALE           		(PWM_BASE + 0x0000)
#define PWM0_CNT                		(PWM_BASE + 0x0004)
#define PWM0_DVD                		(PWM_BASE + 0x0008)
#define PWM0_PATTERN_LOW        		(PWM_BASE + 0x000C)
#define PWM0_PATTERN_HEIGHT     		(PWM_BASE + 0x0010)
#define PWM1_PRESCALE           		(PWM_BASE + 0x0014)
#define PWM1_CNT                		(PWM_BASE + 0x0018)
#define PWM1_DVD                		(PWM_BASE + 0x001C)
#define PWM1_PATTERN_LOW        		(PWM_BASE + 0x0020)
#define PWM1_PATTERN_HEIGHT     		(PWM_BASE + 0x0024)
#define PWM2_PRESCALE           		(PWM_BASE + 0x0028)
#define PWM2_CNT                		(PWM_BASE + 0x002C)
#define PWM2_DVD                		(PWM_BASE + 0x0030)
#define PWM2_PATTERN_LOW        		(PWM_BASE + 0x0034)
#define PWM2_PATTERN_HEIGHT     		(PWM_BASE + 0x0038)
                                		
#define PWM0_BASE               		(PWM_BASE)