📄 sc6600d_reg.h
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/******************************************************************************
** File Name: sc6600d.h *
** Author: Jimmy.Jia *
** DATE: 07/03/2004 *
** Copyright: 2004 Spreadtrum, Incoporated. All Rights Reserved. *
** Description: *
** Register address map for the sc6600d chip *
** Reference to the SC6600D control register document *
******************************************************************************
******************************************************************************
** Edit History *
** ------------------------------------------------------------------------- *
** DATE NAME DESCRIPTION *
** 07-03-2003 Jimmy.Jia Create. *
******************************************************************************/
#ifndef _SC6600D_REG_H_
#define _SC6600D_REG_H_
/**---------------------------------------------------------------------------*
** Constant Variables *
**---------------------------------------------------------------------------*/
/*----------Global Registers----------*/
//GREG_BASE 0x8B000000
#define GR_ADCC (GREG_BASE + 0x0000)
#define GR_ADCR (GREG_BASE + 0x0004)
#define GR_GEN0 (GREG_BASE + 0x0008)
#define GR_PCTL (GREG_BASE + 0x000C)
#define GR_IRQ (GREG_BASE + 0x0010)
#define GR_ICLR (GREG_BASE + 0x0014)
#define GR_GEN1 (GREG_BASE + 0x0018)
#define GR_PCMCIA_CTL (GREG_BASE + 0x001C)
#define GR_HWRST (GREG_BASE + 0x0020)
#define GR_PLL_MN (GREG_BASE + 0x0024)
#define GR_LDO_CTL0 (GREG_BASE + 0x0028)
#define GR_GEN2 (GREG_BASE + 0x002C)
#define GR_ARM_BOOT_ADDR (GREG_BASE + 0x0030)
#define GR_DSP_STSTE (GREG_BASE + 0x0034)
#define GR_LDO_CTL1 (GREG_BASE + 0x0038)
#define GR_ANATST_CTL (GREG_BASE + 0x003C)
#define GR_SYS_ALM (GREG_BASE + 0x0040)
#define GR_BUSCLK_ALM (GREG_BASE + 0x0044)
#define GR_MCU_MISC_EN (GREG_BASE + 0x0048)
#define GR_KPD_SOFT_RST (GREG_BASE + 0x004C)
#define GR_EXT_MEM_DLY (GREG_BASE + 0x0050)
#define GR_EXT_MEM_DLY_CS3 (GREG_BASE + 0x0054)
/*----------Chip Pin Control Register----------*/
//PIN_CTL_BASE 0x8C000000
#define CPC_SEL_REG0 (PIN_CTL_BASE + 0x0000)
#define CPC_SEL_REG1 (PIN_CTL_BASE + 0x0004)
#define CPC_SEL_REG2 (PIN_CTL_BASE + 0x0008)
#define CPC_SEL_REG3 (PIN_CTL_BASE + 0x000C)
#define CPC_SEL_REG4 (PIN_CTL_BASE + 0x0010)
#define CPC_SEL_REG5 (PIN_CTL_BASE + 0x0014)
#define CPC_SEL_REG6 (PIN_CTL_BASE + 0x0018)
#define CPC_SEL_REG7 (PIN_CTL_BASE + 0x001C)
#define CPC_SEL_REG8 (PIN_CTL_BASE + 0x0020)
#define CPC_SEL_REG9 (PIN_CTL_BASE + 0x0024)
#define CPC_SEL_REG10 (PIN_CTL_BASE + 0x0028)
#define CPC_SEL_REG11 (PIN_CTL_BASE + 0x002C)
#define CPC_SEL_REG12 (PIN_CTL_BASE + 0x0030)
#define CPC_SEL_REG13 (PIN_CTL_BASE + 0x0034)
#define CPC_SEL_REG14 (PIN_CTL_BASE + 0x0038)
#define CPC_SEL_REG15 (PIN_CTL_BASE + 0x003C)
#define CPC_SEL_REG16 (PIN_CTL_BASE + 0x0040)
#define CPC_SEL_REG17 (PIN_CTL_BASE + 0x0044)
#define CPC_SEL_REG18 (PIN_CTL_BASE + 0x0048)
#define CPC_SEL_REG19 (PIN_CTL_BASE + 0x004C)
#define CPC_DRV_REG0 (PIN_CTL_BASE + 0x0064)
#define CPC_DRV_REG1 (PIN_CTL_BASE + 0x0068)
#define CPC_DRV_REG2 (PIN_CTL_BASE + 0x006C)
#define CPC_DRV_REG3 (PIN_CTL_BASE + 0x0070)
#define CPC_DRV_REG4 (PIN_CTL_BASE + 0x0074)
#define CPC_DRV_REG5 (PIN_CTL_BASE + 0x0078)
#define CPC_DRV_REG6 (PIN_CTL_BASE + 0x007C)
#define CPC_DRV_REG7 (PIN_CTL_BASE + 0x0080)
#define CPC_DRV_REG8 (PIN_CTL_BASE + 0x0084)
#define CPC_DRV_REG9 (PIN_CTL_BASE + 0x0088)
#define CPC_DRV_REG10 (PIN_CTL_BASE + 0x008C)
#define CPC_DRV_REG11 (PIN_CTL_BASE + 0x0090)
#define CPC_DRV_REG12 (PIN_CTL_BASE + 0x0094)
#define CPC_DRV_REG13 (PIN_CTL_BASE + 0x0098)
#define CPC_DRV_REG14 (PIN_CTL_BASE + 0x009C)
#define CPC_DRV_REG15 (PIN_CTL_BASE + 0x00A0)
#define CPC_DRV_REG16 (PIN_CTL_BASE + 0x00A4)
#define CPC_DRV_REG17 (PIN_CTL_BASE + 0x00A8)
#define CPC_DRV_REG18 (PIN_CTL_BASE + 0x00AC)
#define CPC_DRV_REG19 (PIN_CTL_BASE + 0x00B0)
#define CPC_WPU_REG0 (PIN_CTL_BASE + 0x00C8)
#define CPC_WPU_REG1 (PIN_CTL_BASE + 0x00CC)
#define CPC_WPU_REG2 (PIN_CTL_BASE + 0x00D0)
#define CPC_WPU_REG3 (PIN_CTL_BASE + 0x00D4)
#define CPC_WPU_REG4 (PIN_CTL_BASE + 0x00D8)
#define CPC_WPU_REG5 (PIN_CTL_BASE + 0x00DC)
#define CPC_WPU_REG6 (PIN_CTL_BASE + 0x00E0)
#define CPC_WPU_REG7 (PIN_CTL_BASE + 0x00E4)
#define CPC_WPU_REG8 (PIN_CTL_BASE + 0x00E8)
#define CPC_WPU_REG9 (PIN_CTL_BASE + 0x00EC)
#define CPC_SIM_WPU (PIN_CTL_BASE + 0x00EC)
#define CPC_CTL_REG0 (PIN_CTL_BASE + 0x00F8)
//The corresponding bit of all INT_CTL registers.
#define INTCTL_UART_SLEEP_IRQ (1 << 0)
#define INTCTL_SOFT_IRQ (1 << 1)
#define INTCTL_COMMRX (1 << 2)
#define INTCTL_COMMTX (1 << 3)
#define INTCTL_CNT1_IRQ (1 << 4)
#define INTCTL_CNT2_IRQ (1 << 5)
#define INTCTL_GPIO_IRQ (1 << 6)
#define INTCTL_RTC_IRQ (1 << 7)
#define INTCTL_KPD_IRQ (1 << 8)
#define INTCTL_I2C_IRQ (1 << 9)
#define INTCTL_SIM_IRQ (1 << 10)
#define INTCTL_UART0_IRQ (1 << 11)
#define INTCTL_UART1_IRQ (1 << 12)
#define INTCTL_DSP_IRQ (1 << 13)
#define INTCTL_ADC_IRQ (1 << 14)
#define INTCTL_GEA_POOL_IRQ (1 << 15)
#define INTCTL_SYST_IRQ (1 << 16)
#define INTCTL_PCM_IRQ (1 << 17)
#define INTCTL_UART2_IRQ (1 << 18)
#define INTCTL_SPK_IRQ (1 << 19)
#define INTCTL_DMA_IRQ (1 << 20)
#define INTCTL_VBC_IRQ (1 << 21)
#define INTCTL_BM0_IRQ (1 << 22)
#define INTCTL_BM1_IRQ (1 << 23)
#define INTCTL_BM2_IRQ (1 << 24)
#define INTCTL_BM3_IRQ (1 << 25)
#define INTCTL_BM4_IRQ (1 << 26)
#define INTCTL_BM5_IRQ (1 << 27)
#define INTCTL_BM6_IRQ (1 << 28)
#define INTCTL_BM7_IRQ (1 << 29)
#define INTCTL_WDG_IRQ (1 << 30)
#define INTCTL_PBINT_IRQ (1 << 31)
#define INTCTL_ICLR_ALL 0xFFFFFFFF
/*
the GEN0 register bit
*/
#define GEN0_WDG_EN BIT_0
#define GEN0_RSVED1 BIT_1
#define GEN0_TIMER_EN BIT_2
#define GEN0_SIM BIT_3 //SIM module enable bit
#define GEN0_I2C BIT_4
#define GEN0_PWMB BIT_5
#define GEN0_PWMA BIT_6
#define GEN0_RTC BIT_7
#define GEN0_KPD BIT_8
#define GEN0_RSVED2 BIT_9
#define GEN0_MCU_DSP_RST BIT_10
#define GEN0_MCU_SOFT_RST BIT_11
#define GEN0_PLLPD_EN BIT_12
#define GEN0_DSP_START_0 BIT_13
#define GEN0_RSVED3 BIT_14
#define GEN0_SYS_POWER_DOWN BIT_15
/*
the GEN1 register bit
*/
#define GEN1_GEA_EN BIT_8
#define GEN1_PLLMN_EN BIT_9
#define GEN1_RSVED1 BIT_10
#define GEN1_REMPAUSE_EN BIT_11
#define GEN1_TEST_MODEP_MCU BIT_12
#define GEN1_SYSCLK_EN BIT_13
#define GEN1_RSVED2 BIT_14
#define GEN1_CLK_26MHZ_EN BIT_15
#define GEN1_ARM_BOOT_MD0 BIT_20
#define GEN1_ARM_BOOT_MD1 BIT_21
#define GEN1_SERCLK_EB0 BIT_22
#define GEN1_SERCLK_EB1 BIT_23
#define GEN1_SERCLK_EB2 BIT_24
#define GEN1_DMA_EB BIT_25
/*
the PCMCIA ctl register bit
*/
#define PCM_EN BIT_4
/*
the BUSCLK ALM register bit
*/
#define ARM_VB_DA0ON BIT_3
#define ARM_VB_DA1ON BIT_4
#define ARM_VB_ADCON BIT_5
#define ARM_VB_ANAON BIT_6
#define ARM_VB_ACC BIT_7
#define CLK_MCU_INV BIT_14
#define MCU_MN_EN BIT_15
/*
Voice Band Codec register bit
*/
//BASE ADDRESS: ARM_VBC_BASE 0x82003000
#define VBCTRL0 (ARM_VBC_BASE+0x0000)
#define VBCTRL1 (ARM_VBC_BASE+0x0004)
#define VBAUX (ARM_VBC_BASE+0x0008)
#define VBDA0 (ARM_VBC_BASE+0x0010)
#define VBDA1 (ARM_VBC_BASE+0x0014)
#define VBAD (ARM_VBC_BASE+0x0018)
#define VBBUFFERSIZE (ARM_VBC_BASE+0x001c)
#define VBTEST (ARM_VBC_BASE+0x0020)
#define VBADBUFFDTA (ARM_VBC_BASE+0x0024)
#define VBANAP (ARM_VBC_BASE+0x0028)
#define VBDABUFFDTA (ARM_VBC_BASE+0x002c)
#define VBNACS (ARM_VBC_BASE+0x0030)
#define VBADCNT (ARM_VBC_BASE+0x0034)
#define VBSTATUS (ARM_VBC_BASE+0x0038)
#define VBDACNT (ARM_VBC_BASE+0x003c)
#define DACOEF0 (ARM_VBC_BASE+0x0040)
#define DACOEF1 (ARM_VBC_BASE+0x0044)
#define DACOEF2 (ARM_VBC_BASE+0x0048)
#define DACOEFTOP (ARM_VBC_BASE+0x004c)
#define VOICE_IIR_CORE (ARM_VBC_BASE+0x0200)
#define COEFRAM127 (ARM_VBC_BASE+0x02fc)
//-----------------------------------------------
//Stop Control Register
#define STOP_CTL_BASE 0x82000000
#define STOP_REMAP_CTL_EN (STOP_REMAP_CTL_BASE + 0x0000) //Write to this register will pause the mcu
//The corresponding bit of TIMER0_CTL/TIMER1_CTL register.
#define TMCTL_CLK1 (0) //prescale timer clk (apb clk) by 1
#define TMCTL_MODE_B (1 << 6) //
#define TMCTL_EN (1 << 7) //enable bit of this timer.
//-----------------------------------------------
//SIM Card Interface Register
//2002-04-10 Raislin.Kong Modify the SIM relative register define
//The corresponding bit of SIM_STS0 register.
#define SIMSTS0_B_RX_FIFO_FULL (1 << 0) //rx fifo data number bigger than rx_int_mark
#define SIMSTS0_B_TX_FIFO_EMPTY (1 << 1) //tx fifo data number bigger than tx_int_mark
#define SIMSTS0_B_RX_PARITY_ERR (1 << 2) //Int status bit for rx parity error
#define SIMSTS0_B_TX_PARITY_ERR (1 << 3) //Int status bit for tx parity error
#define SIMSTS0_B_UNRESP_CARD (1 << 4) //Int status bit for card unresponsive
#define SIMSTS0_B_CARD_IN (1 << 5) //Int status bit for card inserted
#define SIMSTS0_B_CARD_OUT (1 << 6) //Int status bit for card removed
#define SIMSTS0_B_EARLY_ATR (1 << 7) //Int status bit for early answer to reset
#define SIMSTS0_B_ACTIVE_DONE (1 << 8) //Int status bit to show activation is done
#define SIMSTS0_B_RX_TOUT (1 << 9) //Int status bit to show activation is done
//The corresponding bit of SIM_STS1 register.
//Get the RX byte number in the rx fifo,rx_fifo_count--SIM_STS1[3:0]
#define GET_RX_FIFO_COUNT(sim_register_map) ((sim_register_map)->sts1 & 0x001f)
//Get the TX byte number in the TX fifo,rx_fifo_count--SIM_STS1[8:5]
#define GET_TX_FIFO_COUNT(sim_register_map) (((sim_register_map)->sts1 & 0x03e0) >> 5)
#define SIMSTS1_B_CARD_INSERTED (1 << 10) //Reflect of card in input pin
#define SIMSTS1_B_SIM_DATA (1 << 11) //Reflect of sim data io pin
#define SIMSTS1_B_SIM_ACTIVE_STS (1 << 12) //Activation status, 1: activated. 0: not activated.
#define SIMSTS1_B_ACTIVE_ON (1 << 13) //Busy in activation process
#define SIMSTS1_B_DEACTIVE (1 << 14) //Busy in deactivation process
//The corresponding bit of SIM_IE register.
#define SIMIE_B_RX_FULL (1 << 0) //Enable bit for rx full int
#define SIMIE_B_TX_EMPTY (1 << 1) //Enable bit for tx empty int
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