📄 main.s
字号:
;------------------------------------------------------------------------------
;
; COPYRIGHT (C) 2000, 2001 Intel Corporation.
;
; This software as well as the software described in it is furnished under
; license and may only be used or copied in accordance with the terms of the
; license. The information in this file is furnished for informational use
; only, is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
; Except as permitted by such license, no part of this document may be
; reproduced, stored in a retrieval system, or transmitted in any form or by
; any means without the express written consent of Intel Corporation.
;
; FILENAME: main.s
;
; PURPOSE: This file contains the platform dependent startup code. This is
; the first code to run in the system and is responsible for
; dispatching the platform dependent low-level initialization code
; to the POST initialization routine (PlatformMain()).
;
; LAST MODIFIED: $Modtime: $
;------------------------------------------------------------------------------
;
;------------------------------------------------------------------------------
; DATA AREA
;------------------------------------------------------------------------------
;
AREA BlockData, DATA, READWRITE
regset DCD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
;
;------------------------------------------------------------------------------
; CODE AREA
;------------------------------------------------------------------------------
;
AREA Init, CODE, READONLY, ALIGN=5
;
; HEADER FILES
;
; GET target.mac ; Include low-level initialization code macros
GET common.inc ; Common defs
GET platform.mac ; Include platform macros
GET ostInit.mac ; OST macros
GET cp15.mac ; cp15 macros
GET map.inc ; map data
GET main.mac ; Include the local macros
GET main.inc ; Include local definitions
GET regBase.inc ; register addresses
GET error.inc
;
; The following symbols control various features of the low-level
; initialization code.
;
IF :DEF: BOOTABLE ;hzh
RELOCATE_ROM EQU 1 ; Reloate to RAM
ELSE
RELOCATE_ROM EQU 0
ENDIF
ENABLE_INTERRUPTS EQU 1 ; Enable processor interrupts
;USE_OPTIMAL_MEMORY EQU 1 ; Sets to use the TOPT function (Set in build file)
;
; References to external symbols
;
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
; IMPORT XsGetProcessorVersion ; CPU version
IMPORT PlatformMain ; "C" platform main entrypoint
IMPORT DumpProcessorRegisters ; Display the processor registers
;
; Public routines
;
EXPORT MAIN
EXPORT VirtualToPhysical
EXPORT PhysicalToVirtual
; EXPORT GetCpuVersion
EXPORT IsMMUEnabled
EXPORT IsICacheEnabled
EXPORT IsDCacheEnabled
EXPORT InitiateFcs
;
; Main entry point
;
MAIN
ENTRY
;
; Exception vectors
;
b Reset_Handler ; Must be PIC
ldr pc, =Undefined_Handler
ldr pc, =SWI_Handler
ldr pc, =Prefetch_Handler
ldr pc, =Abort_Handler
nop
ldr pc, =IRQ_Handler
ldr pc, =FIQ_Handler
;
; The RESET entry point
;
Reset_Handler
;IF :DEF: BOOTABLE ;hzh
;
; Put the processor into SVC mode with interrupts disabled (IRQ and FIQ).
;
mrs r14,CPSR ; get the processor status
bic r14,r14,#CPSR_Mode_Mask
orr r14,r14,#(CPSR_Mode_SVC:OR:CPSR_Int_Mask)
msr cpsr_cf,r14 ; SVC 32 mode with interrupts disabled
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
; the following code was added here for porting XLLI
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
GET xlli_Mainstone_defs.inc ; Platform defs
GET regBase.inc
GET xlli_Bulverde_defs.inc ; Processor defs
GET xlli_LowLev_mac.mac ; xlli macros
GET map.inc ; Virtual map data
IMPORT xlli_read_SCR
IMPORT xlli_GPIO_init
IMPORT xlli_mem_init
IMPORT xlli_intr_init
IMPORT xlli_clks_init
IMPORT xlli_freq_change
IMPORT xlli_pwrmgr_init
IMPORT xlli_ost_init
IMPORT xlli_initPageTable
IMPORT xlli_MMU_init
IMPORT xlli_goVirtual
IMPORT xlli_icache_enable
IMPORT xlli_setClocks
IMPORT xlli_setBufImp
IMPORT xlli_mem_restart ; Restart memory controller
IMPORT xlli_mem_Tmax ; Sets maximum memory configuration values
IMPORT xlli_mem_Topt ; Sets optimal memory configuration values based on MemClk frequency
bl xlli_read_SCR ; Read the SCR and LCDCR virtual register data
bl xlli_GPIO_init ; Init the GPIO pins to xlli defaults
IF :DEF: BOOTABLE ;hzh, move here
;
; Clear Discrete LEDs and output progress code out to hex LEDs
;
mov r3, #5 ; SDRAM Buffer impedance strength
bl xlli_setBufImp ; Set SDRAM buffer Impedance
bl xlli_mem_init ; Initialize the memory controller
bl xlli_intr_init ; Initialize the interrupt controller
; bl xlli_clks_init ; Initialize the clocks manager
; determine if the board is running from the PC flash or the MB flash.
; if Mainboard, then don't use TOPT functions
ldr r1, =xlli_SCR_data ; r1 gets the address of the data
ldr r0, [r1] ; r0 gets the contents of the address
ands r0, r0, #0x80000000 ; see if bit 31 is set
bne %F2 ; if bit set, then mainboard
; IF :DEF: USE_OPTIMAL_MEMORY ; testing if we want to optimize memory
bl xlli_mem_Tmax
bl xlli_mem_restart
2
; ENDIF
bl xlli_setClocks ; will poke CCCR so must do Frequency Change
bl xlli_freq_change
; determine if the board is running from the PC flash or the MB flash.
; if Mainboard, then don't use TOPT functions
ldr r1, =xlli_SCR_data ; r1 gets the address of the data
ldr r0, [r1] ; r0 gets the contents of the address
ands r0, r0, #0x80000000 ; see if bit 31 is set
bne %F3 ; if bit set, then mainboard
; IF :DEF: USE_OPTIMAL_MEMORY
bl xlli_mem_Topt
bl xlli_mem_restart
; ENDIF
3
bl xlli_pwrmgr_init ; initialize the power manager
bl xlli_ost_init ; initialize the OS timers
;
; Find out what kind of reset this was
;
ldr r0, =PMRCREGS_PHYSICAL_BASE ; get base address of power mgr / reset control regs
ldr r7, [r0, #RCSR_OFFSET] ; get current value of the reset controller status register
mov r3, #xlli_RCSR_ALL ; extract the reset cause bits
and r7, r7, r3
str r3, [r0, #RCSR_OFFSET] ; clear the reset cause bits (they're sticky)
tst r7, #xlli_RCSR_HWR ; determine if this is hardware reset
bne %F33
tst r7, #xlli_RCSR_GPR ; determine if this is gpio reset
ldrne r1, =ERR_RESET_GPR
bne %F31
tst r7, #xlli_RCSR_WDR ; determine if this is watchdog reset
ldrne r1, =ERR_RESET_WDR
bne %F31
tst r7, #xlli_RCSR_SMR ; determine if this is sleep reset
ldrne r1, =ERR_RESET_NONE
bne %F31
; Determine if we have a valid address in PSPR.
ldr r0, =HWConfig_PHYSICAL_ADDR
ldr r0, [r0] ; fetch Hardware configuration data
tst r0, #1
beq %F33
mov pc, r0 ; address is valid, branch to it
31 ; we are not prepared to handle this situation
; issue error msg to hex LED and go into infinite loop
32 mov r1, r1
b %B32 ; Loop forever
;
; Continute with Hardware init
; NOTE: r7 should still contain the reset cause bits
33
ENDIF ; BOOTABLE hzh, move here
;＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝
bl xlli_initPageTable ; Init memory map page table
; Generate Level 1 page table entries
xlli_mapSECTIONS r1, r2, r3, r4, s_cbSDRAM, v_cbSDRAM, \
p_cbSDRAM, SECTION_x0c1b1, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxSDRAM, i_xxSDRAM, \
i_xxSDRAM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_cxSDRAM, v_cxSDRAM, \
p_cxSDRAM, SECTION_x0c1b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxSRAM, i_xxSRAM, \
i_xxSRAM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxPlatformReg, i_xxPlatformReg, \
i_xxPlatformReg, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxProcessorReg, i_xxProcessorReg, \
i_xxProcessorReg, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxBOOTROM, v_xxBOOTROM, \
p_xxBOOTROM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxALTROM, v_xxALTROM, \
p_xxALTROM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxPCMCIA, i_xxPCMCIA, \
i_xxPCMCIA, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxETHERNET, i_xxETHERNET, \
i_xxETHERNET, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxIntSRAM, i_xxIntSRAM, \
i_xxIntSRAM, SECTION_x0c0b0, Level1tab
bl xlli_MMU_init ; Init the MMU
bl xlli_goVirtual ; Fire up the MMU
; NOTE: at this point, the system is in virtual address translation
; mode, and physical addresses are no longer valid!
bl xlli_icache_enable ; Enable I-Cache, D-Cache, BTB
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
; the above code was added here for porting XLLI
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
mov r0, #0x00000001 ; Display pattern: 0x00000001
setHexLED r0, r1
b %F10
LTORG ; Place a literal pool here
10
;
; We have completed the low-level initialization code with MMU enabled. We
; now have to relocate to RAM, setup the stack, initialize the Diagnostic
; Manager runtime environment and jump to the Diagnostic Manager
; initialization code.
IF RELOCATE_ROM = 1
;
; We have completed the low-level initialization code. We now must relocate
; to RAM, setup the stack, initialize the DM runtime environment and
; jump to the POST initialization code.
;
bl CopyROM
mov r2, #0x00000002 ; Display pattern: 0x00000002
setHexLED r2, r3
;
; Switch to RAM.
;
bl StartAtRAM
mov r2, pc
setHexLED r2, r3
ELSE ;hzh
ldr pc, =StartAtRam
nop
nop
nop
nop
nop
StartAtRam
ENDIF ; RELOCATE_ROM
;
; Get the top of the RAM we can use for stack space.
;
ldr r0, =STACK_LOCATION
mov r10, r0 ; Save the top of memory
;
; Now setup the stack.
;
; Enter SYS mode and set up the SYS stack pointer
;
mov r1, #CPSR_Mode_SYS:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter UND mode and set up the UND stack pointer
;
mov r1, #0x1b:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter ABT mode and set up the ABT stack pointer
;
mov r1, #0x17:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter FIQ mode and set up the FIQ stack pointer
;
mov r1, #CPSR_Mode_FIQ:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter IRQ mode and set up the IRQ stack pointer
;
mov r1, #CPSR_Mode_IRQ:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Set up the SVC stack pointer last and return to SVC mode
;
mov r1, #CPSR_Mode_SVC:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
;ENDIF ; BOOTABLE hzh
;===============================================================
mov r0, #0x00000003 ; Display pattern: 0x00000002
setHexLED r0, r1
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ; Zero init base
cmp r0, r1 ; Check that they are different
beq %F30
mov r5, #0x00000004 ; Display pattern: 0x00000004
setHexLED r5, r6
20 cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc %B20
mov r5, #0x00000005 ; Display pattern: 0x00000005
setHexLED r5, r6
30 ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
40 cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc %B40
mov r5, #0x00000006 ; Display pattern: 0x00000006
setHexLED r5, r6
;
; Debug - set all memory to known pattern
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -