xscp15.inc

pxa27x下rtc程序

;----------------------------
; InvalidateITLBEntryM
;
;   Invalidate an Instruction TLB Entry
;   - When memory is remapped, all TLB entries relating to the old 
;       mapping must be invalidated.
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   $addrReg: Will contain MVA identifying the 
;                        Instruction TLB entry to be invalidated
;   Return:  None
;    
;   CP 15, CR8, opcode_2=1, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c5, 1

    MACRO
        InvalidateITLBEntryM    $addrReg
        MCR     CP15,0,$addrReg,CP15InvalidateTLBReg,CP15InvalidateITLBCRm,Op2InvalidateTLBEntry
    MEND


;----------------------------
; InvalidateDTLBEntryM
;
;   Invalidate a Data TLB Entry
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   $addrReg: Will contain MVA identifying the 
;                        Data TLB entry to be invalidated
;   Return:  None
;    
;   CP 15, CR8, opcode_2=1, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c6, 1

    MACRO
        InvalidateDTLBEntryM   $addrReg
        MCR     CP15,0,$addrReg,CP15InvalidateTLBReg,CP15InvalidateDTLBCRm,Op2InvalidateTLBEntry
    MEND


;=========================================================================
; Cache Lock Down.   CP15, CR9.  
;
;   Write-only.
;
;   Notes: This is an MMU-related register
;          Lock/unlock operations on a disabled cache have an undefined effect.
;
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
; 
;   Fetch and Lock I cache line     0b000 0b0001 MVA        MCR p15, 0, Rd, c9, c1, 0
;   Write data cache lock           0b000 0b0010 Set/Clear  MCR p15, 0, Rd, c9, c2, 0
;         register                                 lock mode 
;   Unlock Instruction cache        0b001 0b0001 Ignored    MCR p15, 0, Rd, c9, c1, 1
;   Unlock Data Cache               0b001 0b0010 Ignored    MCR p15, 0, Rd, c9, c2, 1
; 

;----------------------------
; FetchAndLockICacheLineM
;
;   Fetch and lock an instruction cache line from the specified MVA
;   - Avoids the overhead of cache misses when executing instructions 
;       from this address in the future.
;
;   Input:   $addrReg contains target MVA
;   Return:  None
;    
;   CP 15, CR9, opcode_2=0, CRm1
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c1, 0

    MACRO
        FetchAndLockICacheLineM    $addrReg
        MCR     CP15,0,$addrReg,CP15LockCacheReg,CP15LockICacheCRm,Op2LockCache
    MEND


;----------------------------
; EnableDCacheLockModeM
;
;   Begin Data cache lock mode enable by writing a "1" to the 
;   Data Cache Lock Register.  Any fill into the data cache 
;   during this mode gets locked in.
;
;   Notes: 
;     - This is the only way to lock data into the D cache.
;     - Before locking, the programmer must ensure that no part of 
;       the target data range is already resident in the cache. 
;       The Intel XScale core will not refetch such data, which 
;       will result in it not being locked into the cache.
;
;   Input:        None
;   Return:       None
;   Side Effect:  $anyReg = 1
;    
;   CP 15, CR9, opcode_2=0, CRm2, Contents of Rd=1.
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c2, 0

    MACRO
        EnableDCacheLockModeM   $anyReg
        MOV     $anyReg,#1
        MCR     CP15,0,$anyReg,CP15LockCacheReg,CP15LockDCacheCRm,Op2LockCache
    MEND


;----------------------------
; DisableDCacheLockModeM
;
;   End Data cache lock mode enable by writing a "0" to the 
;   Data Cache Lock Register.  Fills to the data cache are
;   not locked in after this command.
;
;   Input:   None
;   Return:  $anyReg = 0
;    
;   CP 15, CR9, opcode_2=0, CRm2, Contents of Rd=0.
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c2, 0

    MACRO
        DisableDCacheLockModeM   $anyReg
        MOV     $anyReg,#0
        MCR     CP15,0,$anyReg,CP15LockCacheReg,CP15LockDCacheCRm,Op2LockCache
    MEND


;----------------------------
; UnlockInstructionCacheM
;
;   Unlock the entire the Instruction Cache.
;       Note: There is no way to unlock a subset of the ICache.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR9, opcode_2=1, CRm1
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c1, 1

    MACRO
        UnlockInstructionCacheM   $anyReg
        MCR     CP15,0,$anyReg,CP15LockCacheReg,CP15LockICacheCRm,Op2UnlockCache
    MEND


;----------------------------
; UnlockDataCacheM
;
;   Unlock the entire Data Cache
;       Note: There is no way to unlock a subset of the DCache.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR9, opcode_2=1, CRm2
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c2, 1

    MACRO
        UnlockDataCacheM   $anyReg
        MCR     CP15,0,$anyReg,CP15LockCacheReg,CP15LockDCacheCRm,Op2UnlockCache
    MEND

 

;=========================================================================
; TLB (Translation Lookaside Buffer) Lock Down.   CP15, CR10.  
;
;   Write-only.
;
;   Notes: This is an MMU-related register
;          Lock/unlock operations when MMU is disabled have an undefined effect.
;          For applicable protocols, see the Memory Management section of the 
;            Intel XScale Core user's manual.
;
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
; 
;   Translate and Lock I TLB entry    0b000 0b0100 MVA        MCR p15, 0, Rd, c10, c4, 0
;   Translate and Lock D TLB entry    0b000 0b1000 MVA        MCR p15, 0, Rd, c10, c8, 0
;   Unlock I TLB                      0b001 0b0100 Ignored    MCR p15, 0, Rd, c10, c4, 1
;   Unlock D TLB                      0b001 0b1000 Ignored    MCR p15, 0, Rd, c10, c8, 1
; 


;----------------------------
; TransAndLockITLB_EntryM
;
;   Translate an MVA to its physical address and lock it into the 
;       Instruction TLB.
;   - Avoids the overhead of TLB misses when executing instructions 
;       from this address in the future.
;
;   Input:   $addrReg: Will contain the MVA to be translated and 
;                           locked in the ITLB.
;   Return:  None
;    
;   CP 15, CR10, opcode_2=0, CRm4
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c4, 0

    MACRO
        TransAndLockITLB_EntryM   $addrReg
        MCR     CP15,0,$addrReg,CP15LockTLBReg,CP15LockITLBCRm,Op2LockTLB
    MEND


;----------------------------
; TransAndLockDTLB_EntryM
;
;   Translate an MVA to its physical address and lock it into the 
;       Data TLB.
;   - Avoids the overhead of TLB misses when accessing data 
;       at this address in the future.
;
;   Input:   $addrReg: Will contain MVA to be translated and 
;                           locked in the DTLB.
;   Return:  None
;    
;   CP 15, CR10, opcode_2=0, CRm8
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c8, 0

    MACRO
        TransAndLockDTLB_EntryM   $addrReg
        MCR     CP15,0,$addrReg,CP15LockTLBReg,CP15LockDTLBCRm,Op2LockTLB
    MEND


;----------------------------
; UnlockInstructionTLBM
;
;   Unlock the entire Instruction Translation Lookaside Buffer.
;       Note: There is no way to unlock a subset of the ITLB.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR10, opcode_2=1, CRm4
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c4, 1

    MACRO
    UnlockInstructionTLBM   $anyReg
    MCR     CP15,0,$anyReg,CP15LockTLBReg,CP15LockITLBCRm,Op2UnlockTLB
    MEND


;----------------------------
; UnlockDataTLBM
;
;   Unlock the entire Data Translation Lookaside Buffer.
;       Note: There is no way to unlock a subset of the DTLB.
;
;   Input:   None
;   Return:       None
;    
;   CP 15, CR10, opcode_2=1, CRm8
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c8, 1

    MACRO
    UnlockDataTLBM   $anyReg
    MCR     CP15,0,$anyReg,CP15LockTLBReg,CP15LockDTLBCRm,Op2UnlockTLB
    MEND


;=========================================================================
;
;   Note: CP15's CR11 and CR12 are reserved.
;


;=========================================================================
; Process ID (PID)  CP15, CR13, no opcode_2 
;
;   Note: This is an MMU-related register
;         
;

;----------------------------
; GetProcessIDM
;
;   Get value of the Process ID (PID) Register.
;
;   Input:   None
;   Return:  $retReg contains existing value
;
;   CP 15, reg 13
;   Nonsymbolic core instruction: 
;       MRC CP15, 0, Rd, c13, c0, 0

    MACRO
        GetProcessIDM    $retReg
        MRC     CP15,0,$retReg,CP15ProcessIDReg,CP15CRm_0,Op2_0
    MEND

;----------------------------
; SetProcessIDM
;
;  Set value of the Process ID (PID) Register.
; 
;  Input:   $setReg contains new value
;  Return:  None
;   
;  CP 15, reg 13
;  Nonsymbolic core instruction: 
;      MCR CP15, 0, Rd, c13, c0, 0

    MACRO
        SetProcessIDM    $setReg
        MCR     CP15,0,$setReg,CP15ProcessIDReg,CP15CRm_0,Op2_0
    MEND


;=========================================================================
;  Breakpoint Registers  CP15, CR14, opcode_2 varies
;
;   Not implemented.
;
;   Note: It is unclear that macros or subroutines 
;         for this purpose would be useful.
;


;=========================================================================
; Coprocessor Access Register  CP15, CR15, opcode_2 = 0, CRm=1
;
;   - Read/Write
;

;----------------------------
; GetCoprocessorAccessM
;
;   Get value of the Coprocessor Access Register.
; 
;   Input:   None
;   Return:  $retReg contains existing value
;
;   CP 15, reg 15, opcode_2 = 0, CRm=1
;   Nonsymbolic core instruction: 
;       MRC CP15, 0, Rd, c15, c1, 0

    MACRO
    GetCoprocessorAccessM   $retReg

    MRC     CP15,0,$retReg,CP15CoprocessorAccessReg,CP15CoprocessorAccessCRm,Op2_0
    ; Zero undefined bits, including those undefined for Cotulla
    BIC     $retReg,$retReg,#0xff000000
    BIC     $retReg,$retReg,#0x00ff0000
    BIC     $retReg,$retReg,#0x0000df00
    BIC     $retReg,$retReg,#0x000000fe
    MEND


;----------------------------
; SetCoprocessorAccessM
;
;   Set value of the Coprocessor Access Register.
; 
;   Input:   $setReg contains new value
;   Return:  None
;    
;   CP 15, reg 15, opcode_2 = 0, CRm=1
;   Nonsymbolic core instruction: 
;       MCR CP15, 0, Rd, c15, c1, 0

    MACRO
    SetCoprocessorAccessM    $setReg
    ; Zero undefined bits, including those undefined for Cotulla
    BIC     $setReg,$setReg,#0xff000000
    BIC     $setReg,$setReg,#0x00ff0000
    BIC     $setReg,$setReg,#0x0000df00
    BIC     $setReg,$setReg,#0x000000fe
    MCR     CP15,0,$setReg,CP15CoprocessorAccessReg,CP15CoprocessorAccessCRm,Op2_0
    MEND

;=========================================================================
;  Utility macros
;

;----------------------------
; EnableDCacheM
;
;   Enable the Data Cache, using necessary protections.
;
;   From the code example in the Intel XScale Core user's manual.
;
;   Input:        None
;   Return:       None
;   Side Effects: $anyReg undefined
;   Assumptions:  MMU already enabled
;
;   CP 15, reg 1, opcode_2=0
;   Nonsymbolic core instructions: 
;       MCR p15, 0, $anyReg, c7, c10, 4
;       MRC p15, 0, $anyReg, c1, c0,  0
;       MCR p15, 0, $anyReg, c1, c0,  0


    MACRO
    EnableDCacheM  $anyReg

    ; Drain pending data operations...
    DrainBuffersM  $anyReg      ; MCR p15, 0, $anyReg, c7, c10, 4

    GetARMControlM   $anyReg    ; MRC p15, 0, $anyReg, 1, 0, 0
    ; Enable DCache by setting 慍