xscp15.inc

pxa27x下rtc程序

;       MCR p15, 0, Rd, 2, 0, 0

    MACRO
        SetTransTableBaseM   $setReg
        MCR     CP15,0,$setReg,CP15TransTableBaseReg,CP15CRm_0,Op2_0
        ; Don't zero undefined bits.  If the table is not on a 16K 
        ; boundary, the system won't work anyway.
        CPWAIT  ; Wait for it to happen!
    MEND


;=========================================================================
; Domain Access Control   CP15, CR3
;
;   Note: This is an MMU-related register
;
;   Read/Write
;


;----------------------------
; GetDomainAccessControlM
;
;   Get value of the Domain Access Control Register.
;
;   Input:   None
;   Return:  $retReg: Domain Access Control Register contents
;
;   CP 15, reg 3
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 3, 0, ss0

    MACRO
        GetDomainAccessControlM    $retReg
        MRC     CP15,0,$retReg,CP15DomainAccessControlReg,CP15CRm_0,Op2_0
    MEND


;----------------------------
; SetDomainAccessControlM
;
;   Set value of the Domain Access Control Register.
;
;   Input:   $setReg: New Domain Access Control Register contents
;   Return:  None
;
;   Note: No protection against placing the 0b10 Reserved value in
;           any of the individual domain access control fields.
;
;   CP 15, reg 3
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, 3, 0, 0

    MACRO
        SetDomainAccessControlM    $setReg
        MCR     CP15,0,$setReg,CP15DomainAccessControlReg,CP15CRm_0,Op2_0
    MEND



;=========================================================================
;
; Note: CP15 CR4 is reserved.
;


;=========================================================================
; Fault Status and Address   CP15, CR5 and CR6.  
;
;   - Read only.
;

;----------------------------
; GetFaultStatusM
;
;   Get value of the Fault Status Register.
;
;   Input:   None
;   Return:  R0: Fault Status Register contents
;
;   CP 15, reg 5
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 5, 0, 0

    MACRO
        GetFaultStatusM   $retReg
        MRC     CP15,0,$retReg,CP15_FaultStatusReg,CP15CRm_0,Op2_0
        ; Zero undefined bits
        BIC     $retReg,$retReg,#0xff000000
        BIC     $retReg,$retReg,#0x00ff0000
        BIC     $retReg,$retReg,#0x0000f900
    MEND


;----------------------------
; GetFaultAddressM
;
;   Get value of the Fault Address Register.
;
;   Input:   None
;   Return:  R0: Fault Address Register contents
;
;   CP 15, reg 6
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 6, 0, 0

    MACRO
        GetFaultAddressM   $retReg
        MRC     CP15,0,$retReg,CP15FaultAddressReg,CP15CRm_0,Op2_0
    MEND


;=========================================================================
;  Cache operations.   CP15, CR7.  
;
;   Write-only.
;
;   Notes: This is an MMU-related register
;          Be familiar with warnings, assumptions and usage examples in the  
;            Intel XScale Core user's manual and the specific processor's
;            user's manual.  Especially be aware of the ABSENCE of side 
;            effects.  For example, 
;             - Invalidating a cache or cache line does not unlock it.
;             - Invalidating a single instruction cache line does not 
;               automatically invalidate the Branch Target Buffer, which 
;               must be done separately.
;             - Invalidating the caches and Branch Target Buffer does not 
;               invalidate the Translation Lookaside Buffer
; 
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
; 
;   Invalidate I&D cache & BTB      0b000 0b0111 Ignored MCR p15, 0, Rd, c7, c7,  0
;   Invalidate I cache & BTB        0b000 0b0101 Ignored MCR p15, 0, Rd, c7, c5,  0
;   Invalidate I cache line         0b001 0b0101 MVA     MCR p15, 0, Rd, c7, c5,  1
;   Invalidate D cache              0b000 0b0110 Ignored MCR p15, 0, Rd, c7, c6,  0
;   Invalidate D cache line         0b001 0b0110 MVA     MCR p15, 0, Rd, c7, c6,  1
;   Clean D cache line              0b001 0b1010 MVA     MCR p15, 0, Rd, c7, c10, 1
;   Drain Write (& Fill) Buffer     0b100 0b1010 Ignored MCR p15, 0, Rd, c7, c10, 4
;   Invalidate Branch Target Buffer 0b110 0b0101 Ignored MCR p15, 0, Rd, c7, c5,  6
;   Allocate Line in the Data Cache 0b101 0b0010 MVA     MCR p15, 0, Rd, c7, c2,  5


;----------------------------
; InvalidIAndDCachesAndBTBM
;
;   Invalidate both the Instruction and Data caches, 
;       plus the Branch Target Buffer.
;   - Individual cache lines can be invalidated using other commands.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR7, opcode_2=0, CRm7
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c7, 0

    MACRO
        InvalidIAndDCachesAndBTBM    $anyReg
        MCR     CP15,0,$anyReg,CP15CacheOpsReg,CP15InvalidIAndDCacheCRm,Op2_0
    MEND


;----------------------------
; InvalidateICacheAndBTBM
;
;   Invalidate the Instruction cache, plus the Branch Target Buffer.
;   - Individual cache lines can be invalidated using other commands.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR7, opcode_2=0, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c5, 0

    MACRO
        InvalidateICacheAndBTBM    $anyReg
        MCR     CP15,0,$anyReg,CP15CacheOpsReg,CP15InvalidICacheCRm,Op2_0
    MEND


;----------------------------
; InvalidateDCacheM
;
;   Invalidate the Data cache
;   - Individual cache lines can be invalidated using other commands.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR7, opcode_2=0, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c6, 0

    MACRO
        InvalidateDCacheM     $anyReg
        MCR     CP15,0,$anyReg,CP15CacheOpsReg,CP15InvalidDCacheCRm,Op2_0
    MEND


;----------------------------
; InvalidateICacheLineM
;
;   Invalidate a line in the Instruction cache.
;   - Does not invalidate the BTB.
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   R0: MVA identifying the Instruction cache line to be invalidated
;   Return:  None
;    
;   CP 15, CR7, opcode_2=1, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c5, 1

    MACRO
        InvalidateICacheLineM   $addrReg
        MCR     CP15,0,$addrReg,CP15CacheOpsReg,CP15InvalidICacheCRm,Op2_1
    MEND


;----------------------------
; InvalidateDCacheLineM
;
;   Invalidate a line in the Data cache
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   $addrReg: Will contain MVA identifying the 
;                        Data cache line to be invalidated
;   Return:  None
;    
;   CP 15, CR7, opcode_2=1, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c6, 1

    MACRO
        InvalidateDCacheLineM   $addrReg
        MCR     CP15,0,$addrReg,CP15CacheOpsReg,CP15InvalidDCacheCRm,Op2_1
    MEND


;----------------------------
; CleanDCacheLineM
;
;   Clean a line in the Data cache
;
;   - Updates external memory with data from the "dirty" portions of 
;       a specific line in data cache and clears the dirty bits.
;   - Leaves line marked as clean but still valid.
;
;   Input:   R0: MVA identifying the Data cache line to be cleaned
;   Return:  None
;    
;   CP 15, CR7, opcode_2=1, CRm10
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c10, 1

    MACRO
        CleanDCacheLineM    $addrReg
        MCR     CP15,0,$addrReg,CP15CacheOpsReg,CP15CleanDCacheCRm,Op2_1
    MEND


;----------------------------
; DrainBuffersM
;
;   Drain the write and fill buffers of the cache.
;
;   - Guarantees that before the next instruction executes, 
;     core data requests to external memory have completed.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR7, opcode_2=4, CRm10
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c10, 4

    MACRO
        DrainBuffersM  $anyReg
        MCR     CP15,0,$anyReg,CP15CacheOpsReg,CP15DrainCacheCRm,Op2_4
    MEND


;----------------------------
; InvalidateBTBM
;
;   Invalidate the Branch Target Buffer.
;   - Needed after invalidating individual instruction cache lines.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR7, opcode_2=6, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c5, 6

    MACRO
        InvalidateBTBM     $anyReg
        MCR     CP15,0,$anyReg,CP15CacheOpsReg,CP15InvalidICacheCRm,Op2_6
    MEND

;----------------------------
; AllocateDCacheLineM
;
;   Allocate a line in the Data cache
;
;   - Allocates a tag into the data cache specified by bits 
;     [31:5] of $addrReg.  If a valid dirty line (with a different 
;     MVA) already exists at this location it will be evicted.
;
;   WARNING: This command has limited uses and many conditions of
;            safe use.  See the Cache Functions section and Data Cache 
;            section of the Core user's guide for details.
;
;   Input:   $addrReg bits[31:5]: Will contain MVA identifying the Data 
;                                   cache tag to be allocated.
;   Return:  None
;    
;   CP 15, CR7, opcode_2=5, CRm2
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c2, 5

    MACRO
        AllocateDCacheLineM    $addrReg 
        ; Clear out lower 5 bits, not used.
        BIC     $addrReg,$addrReg,#0x0000000001f
        MCR     CP15,0,$addrReg,CP15CacheOpsReg,CP15AllocateDCacheLineCRm,Op2_5
    MEND


;=========================================================================
; TLB (Translation Lookaside Buffer) operations.   CP15, CR8.  
;
;   Write-only.
;
;   Notes: This is an MMU-related register
;          Invalidating a TLB entry or the entire TLB does not unlock it.
;           
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
;
;   Invalidate I&D TLB              0b000 0b0111 Ignored MCR p15, 0, Rd, c8, c7, 0
;   Invalidate I TLB                0b000 0b0101 Ignored MCR p15, 0, Rd, c8, c5, 0
;   Invalidate I TLB entry          0b001 0b0101 MVA     MCR p15, 0, Rd, c8, c5, 1
;   Invalidate D TLB                0b000 0b0110 Ignored MCR p15, 0, Rd, c8, c6, 0
;   Invalidate D TLB entry          0b001 0b0110 MVA     MCR p15, 0, Rd, c8, c6, 1
; 

;----------------------------
; InvalidateIandDTLBsM
;
;   Invalidate both the Instruction and Data TLBs
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - Individual TLB entries may be invalidated by using other commands to CP15.
;
;   Input:         None
;   Return:        None
;   Side Effects:  R0 undefined
;    
;   CP 15, CR8, opcode_2=0, CRm7
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c7, 0

    MACRO
        InvalidateIandDTLBsM   $anyReg
        MCR     CP15,0,$anyReg,CP15InvalidateTLBReg,CP15InvalidateIandDTLBsCRm,Op2InvalidateEntireTLB
        CPWAIT  ; Wait for it to happen!
        
    MEND

;----------------------------
; InvalidateITLBM
;
;   Invalidate the Instruction TLB
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - Individual TLB entries may be invalidated by using other commands to CP15.
;
;   Input:         None
;   Return:        None
;   Side Effects:  R0 undefined
;    
;   CP 15, CR8, opcode_2=0, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c5, 0

    MACRO
        InvalidateITLBM  $anyReg
        MCR     CP15,0,$anyReg,CP15InvalidateTLBReg,CP15InvalidateITLBCRm,Op2InvalidateEntireTLB
        CPWAIT  ; Wait for it to happen!
    MEND


;----------------------------
; InvalidateDTLBM
;
;   Invalidate the Data TLB
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - Individual TLB entries may be invalidated by using other commands to CP15.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR8, opcode_2=0, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c6, 0

    MACRO
        InvalidateDTLBM   $anyReg
        MCR     CP15,0,$anyReg,CP15InvalidateTLBReg,CP15InvalidateDTLBCRm,Op2InvalidateEntireTLB
    MEND