xscp15.inc

pxa27x下rtc程序

;----------------------------------------------------------------------
;   Copyright (C) 2000 Intel Corp.
;
;   Filename XsCp15.inc
;
;   This file contains Intel(R) Xscale(TM) Microarchitecture 
;       Coprocessor 15 constants and macros.
;
;   Requires XsCP.inc
;
;    2000-12-11: 14:30 EST
;
;

;/////////////////////////////////////////////////////////////////////////
;
;   List of macros in alphabetical order
;
;   Note:   EnableMMU is not implemented as a macro, but only as a subroutine.
;           Other utilities are implemented only as subroutines, so as to avoid 
;               the complexity of dealing with internal labels.
;           For these subroutines, see XsCp15.s
;
;   AllocateDCacheLineM
;   CleanDCacheFastM
;   CleanDCacheSlowM
;   CleanDCacheLineM
;   CPWAIT
;   CreateDataRAMM
;   DisableDCacheM
;   DisableDCacheLockModeM
;   DrainBuffersM
;   EnableDCacheLockModeM
;   EnableDCacheM
;   FetchAndLockICacheLineM
;   GetARMControlM
;   GetAuxControlM
;   GetCacheTypeM
;   GetCoprocessorAccessM
;   GetDomainAccessControlM
;   GetFaultAddressM
;   GetFaultStatusM
;   GetProcessIDM
;   GetProcVersionM
;   GetTransTableBaseM
;   InvalidateBTBM
;   InvalidateDCacheLineM
;   InvalidateDCacheM
;   InvalidateDTLBEntryM
;   InvalidateDTLBM
;   InvalidateIandDTLBsM
;   InvalidateICacheAndBTBM
;   InvalidateICacheLineM
;   InvalidateITLBEntryM
;   InvalidateITLBM
;   InvalidIAndDCachesAndBTBM
;   SetARMControlM
;   SetAuxControlM
;   SetCoprocessorAccessM
;   SetDomainAccessControlM
;   SetProcessIDM
;   SetTransTableBaseM
;   TransAndLockDTLB_EntryM
;   TransAndLockITLB_EntryM
;   UnlockDataCacheM
;   UnlockDataTLBM
;   UnlockInstructionCacheM
;   UnlockInstructionTLBM
;

;/////////////////////////////////////////////////////////////////////////
;
;   Symbol definitions for Coprocessor 15 and Coprocessor 15 Registers 
;
;   Note: Multiple symbols for the same register may occur.  The names are
;         defined for usage in the MRC/MCR commands that access various
;         Coprocessor 15 functions.
;

CP15    CP  15 ; Alias for Coprocessor 15 (rather than just "p15")

;
;  CP15, Reg 0
;

CP15IDReg                   CN  0

Op2ProcID                   EQU 0
Op2CacheType                EQU 1

;
;  CP15, Reg 1
;

CP15ArmControlReg           CN  1
; Some bit masks for ARM Control Register
CP15MMUEnable               EQU 1
CP15AlignmentFaultEnable    EQU 1:SHL:1
CP15DCacheEnable            EQU 1:SHL:2
CP15BigEndianEnable         EQU 1:SHL:7
CP15SystemProtection        EQU 1:SHL:8
CP15RomProtection           EQU 1:SHL:9
CP15SRMask                  EQU 3:SHL:8
CP15BranchTgtBufEnable      EQU 1:SHL:11
CP15ICacheEnable            EQU 1:SHL:12
CP15RelocateVectorTable     EQU 1:SHL:13



CP15AuxControlReg           CN  1

;
;  CP15, Reg 2
;

CP15TransTableBaseReg       CN  2

;
;  CP15, Reg 3
;

CP15DomainAccessControlReg  CN  3

;
;  CP15, Reg 5
;

CP15_FaultStatusReg         CN  5

;
;  CP15, Reg 6
;

CP15FaultAddressReg         CN  6

;
;  CP15, Reg 7
;

CP15CacheOpsReg             CN  7

CP15AllocateDCacheLineCRm   CN  2
CP15InvalidICacheCRm        CN  5
CP15InvalidDCacheCRm        CN  6
CP15InvalidIAndDCacheCRm    CN  7
CP15CleanDCacheCRm          CN  10
CP15DrainCacheCRm           CN  10

;
;  CP15, Reg 8
;

CP15InvalidateTLBReg        CN  8

CP15InvalidateITLBCRm       CN  5
CP15InvalidateDTLBCRm       CN  6
CP15InvalidateIandDTLBsCRm  CN  7

Op2InvalidateEntireTLB      EQU 0
Op2InvalidateTLBEntry       EQU 1

;
;  CP15, Reg 9
;

CP15LockCacheReg            CN  9

CP15LockICacheCRm           CN  1
CP15LockDCacheCRm           CN  2

Op2LockCache                EQU 0
Op2UnlockCache              EQU 1

;
;  CP15, Reg 10
;

CP15LockTLBReg              CN  10

CP15LockITLBCRm             CN  4
CP15LockDTLBCRm             CN  8

Op2LockTLB                  EQU 0
Op2UnlockTLB                EQU 1

;
;  CP15, Reg 13
;

CP15ProcessIDReg            CN  13

;
;  CP15, Reg 15
;

CP15CoprocessorAccessReg    CN  15

CP15CoprocessorAccessCRm    CN  1


;/////////////////////////////////////////////////////////////////////////
;
;   General Macro Definitions for CP 15 Register Access
;
;   - The M terminator is used for all macros.
;   - When using the macros, the "$xxxReg" macro parameter must be in 
;       {R0..R10} and should normally be R0 or R1.
;

;=========================================================================
; CPWAIT
;
;   Standard macro to let CP15 commands complete before moving to
;   next operation.  Taken from Intel XScale Core user's manual.
;
;   Input:         None
;   Return:        None
;   Side Effects:  R0 undefined
;   
;
;;  The following macro should be used when software needs to be
;;  assured that a CP15 update has taken effect.
;;  It may only be used while in a privileged mode, because it
;;  accesses CP15.

    MACRO
        CPWAIT
        MRC CP15, 0, R0, c2, c0, 0 ; arbitrary read of CP15
        MOV R0, R0 ; wait for it
        SUB PC, PC, #4 ; branch to next instruction
        ; At this point, any previous CP15 writes are
        ; guaranteed to have taken effect.
    MEND


;=========================================================================
; ID & Cache Type
;
;   CP15, CR0, opcod_2=0,1
;
;   Read-only
;

;----------------------------
; GetProcVersionM
;
;   Get processor version info
;
;   Input:   None
;   Return:  $retReg:  ID Register contents
;
;   Note: For first silicon of Cotulla, should be 0x69052000
;
;   CP 15, reg 0, opcode_2=0
;
;   Nonsymbolic core instructions: 
;       MRC p15, 0, Rd, 0, 0, 0

    MACRO
        GetProcVersionM $retReg
        MRC     CP15,0,$retReg,CP15IDReg,CP15IDReg,Op2ProcID
    MEND

;----------------------------
; GetCacheTypeM
;
;   Get cache type info 
;
;   Input:   None
;   Return:  $retReg:  ID Register contents
;
;   CP 15, reg 0, opcode_2=1
;   Nonsymbolic core instructions: 
;       MRC p15, 0, Rd, 0, 0, 1

    MACRO
        GetCacheTypeM  $retReg
        MRC     CP15,0,$retReg,CP15IDReg,CP15IDReg,Op2CacheType
    MEND

;=========================================================================
; Control & Auxiliary Control
;
;   CP15, CR1, opcod_2=0,1
;
;   Read/Write
;


;----------------------------
; GetARMControlM
;
;   Get the value in the ARM Control Register.
;
;   Input:   None
;   Return:  $retReg:  ARM Control Register contents
;
;   CP 15, reg 1, opcode_2=0
;   Nonsymbolic core instructions: 
;       MRC p15, 0, Rd, 1, 0, 0

    MACRO
        GetARMControlM   $retReg
        MRC     CP15,0,$retReg,CP15ArmControlReg,CP15CRm_0,Op2_0
        ; Zero reserved bits
        BIC     $retReg,$retReg,#0xff000000
        BIC     $retReg,$retReg,#0x00ff0000
        BIC     $retReg,$retReg,#0x0000c400
    MEND


;----------------------------
; SetARMControlM
;
;   Set the value of the ARM Control Register.
;
;   Input:   $setReg:  New ARM Control Register contents
;   Return:  None
;
;   CP 15, reg 1, opcode_2=0
;   Nonsymbolic core instructions: 
;       MCR p15, 0, Rd, 1, 0, 0

    MACRO
        SetARMControlM $setReg
        ; Zero reserved bits
        BIC     $setReg,$setReg,#0xff000000
        BIC     $setReg,$setReg,#0x00ff0000
        BIC     $setReg,$setReg,#0x0000c400
        ; Force write-as-one bits
        ORR     $setReg,$setReg,#0000000078
        MCR     CP15,0,$setReg,CP15ArmControlReg,CP15CRm_0,Op2_0
    MEND


;----------------------------
; GetAuxControlM
;
;   Get the value in the Auxiliary Control Register.
;
;   Input:   None
;   Return:  $retReg:  Auxiliary Control Register contents
;
;   CP 15, reg 1, opcode_2=1
;   Nonsymbolic core instructions: 
;       MRC p15, 0, Rd, 1, 0, 1

    MACRO
        GetAuxControlM  $retReg
        MRC     CP15,0,$retReg,CP15AuxControlReg,CP15AuxControlReg,Op2_1
        ; Zero reserved bits
        BIC     $retReg,$retReg,#0xff000000
        BIC     $retReg,$retReg,#0x00ff0000
        BIC     $retReg,$retReg,#0x0000ff00
        BIC     $retReg,$retReg,#0x000000cc
    MEND


;----------------------------
; SetAuxControlM
;
;   Set the value in the Auxiliary Control Register.
;
;   Input:   $setReg:  New Auxiliary Control Register contents
;   Return:  None
;
;   CP 15, reg 1, opcode_2=1
;   Nonsymbolic core instructions: 
;       MCR p15, 0, Rd, 1, 0, 1

    MACRO
        SetAuxControlM $setReg
        ; Zero reserved bits
        BIC     $setReg,$setReg,#0xff000000
        BIC     $setReg,$setReg,#0x00ff0000
        BIC     $setReg,$setReg,#0x0000ff00
        BIC     $setReg,$setReg,#0x000000cc
        MCR     CP15,0,$setReg,CP15AuxControlReg,CP15CRm_0,Op2_1
    MEND


;=========================================================================
; Translation Table Base   CP15, CR2
;
;   Note: This is an MMU-related register
;
;   Read/Write
;

;----------------------------
; GetTransTableBaseM
;
;   Get physical address of the base of the first-level translation
;       table as known to the MMU. Sometimes called "page table"
;
;   Input:   None
;   Return:  $retReg:  Translation Table Base Register contents
;
;   CP 15, reg 2
;   Nonsymbolic core instructions: 
;   MRC p15, 0, Rd, 2, 0, 0

    MACRO
        GetTransTableBaseM   $retReg
        MRC     CP15,0,$retReg,CP15TransTableBaseReg,CP15CRm_0,Op2_0
        ; Zero undefined bits
        BIC     $retReg,$retReg,#0x00003f00
        BIC     $retReg,$retReg,#0x000000ff
    MEND


;----------------------------
; SetTransTableBaseM
;
;   Put physical address of the base of the first-level translation
;       table into the Translation Table Base Register so that the 
;       MMU sees it.  Sometimes called "page table" base.
;
;   Input:   $setReg:  Translation Table base physical address
;   Return:  None
;
;   CP 15, reg 2
;   Nonsymbolic core instruction: