xscp15.s

pxa27x下rtc程序

    ;   R0 is re-used as a target for the throw-away data move.  Its original
    ;       value is now irrelevant.
    ;
    MOV R2, #64
CleanDCacheLoop2
    LDR R0,[R1],#32 ; Load and increment to next cache line
    SUBS R2, R2, #1 ; Decrement loop count
    BNE CleanDCacheLoop2      ; Back to loop 2 top if nonzero
    ;
    ; Invalidate the data cache and mini-data cache
    InvalidateDCacheM    R0     ; MCR p15, 0, Rd, c7, c6, 0

	MOV     pc,lr

; End XsCleanDCache(), fast

    ELSE
    ; DEF: DEDICATED_CACHE_CLEANING_MEM
    ; No memory blocks are dedicated to cleaning the data caches

;----------------------------
; void XsCleanDCache (UINT32 dcacheBufP, UINT32 miniDCacheBufP) 
; ; slow version
;
;   Global Clean/Invalidate THE DATA CACHE,
;       not using the fastest possible method.
;
;   Use this method if there are no cacheable memory regions 
;   reserved for the data cache cleaning operations.
;
;   Slight modification of the example presented in the Intel XScale
;   Core user's manual (R0 and R1 both contain addresses, and the
;   number of cache writes is doubled because of the lack of dedicated
;   resources).
;
;   Input:  
;       R0: Contains the virtual address of any 128K region of cacheable
;           virtual memory.  This region does not need to be backed by 
;           physical memory.
;       R1: Contains the virtual address of a 4K region of cacheable
;           memory reserved for cleaning the Mini-data Cache.
;           This region needs to be backed by physical memory.
;           If the Mini-data Cache is not used in the system, any 4K 
;           block of virtual memory may be used so long as it is  
;           backed by physical memory.
;
;   Return:       None
;   Side Effect:  R0, R1, R2 undefined
;
    ALIGN
    EXPORT  XsCleanDCache
XsCleanDCache

    MOV R2, #2048   ; Two times the number of data cache lines.  
CleanDCacheLoop1
    ; Allocate a line at the virtual address specified by R0.
    AllocateDCacheLineM R0  ; MCR p15, 0, R0, c7, c2, 5
    ADD R0, R0, #32 ; Increment the address in R0 to the next cache line
    SUBS R2, R2, #1 ; Decrement loop count
    BNE CleanDCacheLoop1       ; Back to loop 1 top if nonzero
    ;
    ;   Clean the Mini-data Cache
    ;   Can抰 use line-allocate command, so cycle 4KB of unused data through.
    ;   R1 contains the virtual address of a region of cacheable memory 
    ;       reserved for cleaning the Mini-data Cache
    ;   R2 is the loop count. Iterate 128 times which is the twice the  
    ;       number of lines in the Mini-data Cache.
    ;   R0 is re-used as a target for the throw-away data move.  Its original
    ;       value is now irrelevant.
    ;
    MOV R2, #64
CleanDCacheLoop2
    LDR R0,[R1],#32 ; Load and increment to next cache line
    SUBS R2, R2, #1 ; Decrement loop count
    BNE CleanDCacheLoop2      ; Back to loop 2 top if nonzero
    ;
    ; Invalidate the data cache and mini-data cache
    InvalidateDCacheM    R0     ; MCR p15, 0, Rd, c7, c6, 0

	MOV     pc,lr


    ; Not DEF: DEDICATED_CACHE_CLEANING_MEM
    ; End of Yes or No memory blocks dedicated to cleaning the data caches
    ENDIF

; End XsCleanDCache(), slow

;----------------------------
; void XsEnableMMU (void)
; 
;   Enable the MMU and continue from remapped RAM.
;
;   Input:          None
;   Return:         None
;   Side Effects:   R0, R1, R2 undefined
;                   Includes an adjustment for code that might be 
;                       executing at a different physical address 
;                       than virtual address (see Assumptions 3).
;                   Instruction caching is enabled (needed to support
;                       different physical and virtual addresses).
;                   Data caching is enabled.
;                   Delay for activation of setting
;    
;   Assumptions:    1) Translation table is in place.
;                   2) Translation table base register is programmed.
;                   3) The MMU was not already enabled.  This permits
;                       skipping the drain operation.
;                   4) Note that if the original physical and target
;                       virtual addresses of the code differ, it must 
;                       be fully relocatable up to this point.  (All 
;                       branches and data references must be
;                       PC-relative.)  These addresses differ if the 
;                       address for which it is linked and into which it
;                       is programmed in ROM or Flash are not the same.
;
;

; Note:
;   The MMU, instruction cache, and data/mini-data cache may be 
;   enabled/disabled independently.  The instruction cache can be 
;   enabled with the MMU enabled or disabled. However, the data cache
;   can only be enabled when the MMU is enabled. Enabling the data caches
;   with the MMU disabled will cause undefined results.
;

    ALIGN
    EXPORT  XsEnableMMU
XsEnableMMU

    ; First, some possibly unnecessary cleanup.
    ; Invalidate caches and Trans Lookaside Buf
    InvalidIAndDCachesAndBTBM    R0     ; MCR p15, 0, R0, c7, c7, 0
    InvalidateIandDTLBsM         R0     ; MCR p15, 0, R0, c8, c7, 0

    ; Set up for address correction.  Get difference between linked 
    ;   and address execution address.  Store in R2.
CheckPointAddress
                                        ; Actual execution address at 
	sub	r0, pc, #8                      ;  CheckPointAddress label into R0
	ldr	r1, =CheckPointAddress          ; Linked value of CheckPointAddress
	sub	r2, r0, r1

    ; Turn on the instruction cache, which is needed for the
    ;   transition from running out of Flash to running out of
    ;   RAM if the physical and virtual execution addresses
    ;   are different.
    GetARMControlM   R0                 ; MRC p15, 0, R0, 1, 0, 0
    ORR R0, R0, #CP15ICacheEnable       ; set enable bit for instruction cache
    SetARMControlM   R0                 ; MCR p15, 0, R0, 1, 0, 0

    ORR R0, R0, #(CP15MMUEnable:OR:CP15DCacheEnable) ;  MMU and data cache, too.
	; Next critical code section must fit in single cache block of 32 bytes
    ALIGN	32
    ; Turn on the MMU and data cache
    SetARMControlM   R0                 ; MCR p15, 0, R0, 1, 0, 0
    CPWAIT
	; Adjust for execution address diff. and return
	sub	pc,lr,r2		                

; End XsEnableMMU()


;----------------------------
; void XsEnableDCache (void)
;
;   Enable the Data Cache, using necessary protections.
;
;   From the code example in the Intel XScale Core user's manual.
;
;   Input:          None
;   Return:         None
;   Side Effects:   R0 undefined
;   Assumptions:    MMU already enabled
;

    ALIGN
    EXPORT  XsEnableDCache
XsEnableDCache
    EnableDCacheM  R0
	MOV     pc,lr                   ; return


;----------------------------
; void XsDisableDCache (void)
;
;   Disable the Data Cache, using necessary protections.
;
;   Input:        None
;   Return:       None
;   Side Effects: R0 undefined
;
;   CP 15, reg 1, opcode_2=0
;   Nonsymbolic core instructions: 
;       MCR p15, 0, $anyReg, c7, c10, 4
;       MRC p15, 0, $anyReg, c1, c0,  0
;       MCR p15, 0, $anyReg, c1, c0,  0
;
;   NOTE from the from Intel XScale Core user's manual:
;              Operation When Data Caching is Disabled
;     The data/mini-data cache is still accessed even though it is 
;     disabled. If a load hits the cache it will return the requested 
;     data to the destination register. If a store hits the cache, 
;     the data is written into the cache. Any access that misses the 
;     cache will not allocate a line in the cache when it抯 disabled,
;     even if the MMU is enabled and the memory region抯 cacheability 
;     attribute is set.
;
;   (Therefore, effective disabling of the data cache requires additional
;   action.  That action is performing the global clean and invalidate 
;   procedure using dedicated virtual memory locations.  This is exampled  
;   in the Intel XScale Core user's manual and implemented in CleanDCache() 
;   (fast version).)
;

    ALIGN
    EXPORT  XsDisableDCache
XsDisableDCache
    DisableDCacheM  R0
	MOV     pc,lr                   ; return


;----------------------------
; void XsLockDataIntoCache (UINT32 lineCount, UINT32 regionBaseAddr)
; 
;   Lock a region of memory into the Data Cache
;   Based on  the code example in the Intel XScale Core user's manual.
;
;   Input:          R0:  The number of 32-byte lines to lock into
;                           the data cache 
;                   R1:  The virtual address of a region of memory
;                           to lock, configured with C=1 and B=1
;   Return:         None
;
;   Side Effects:   R0, R1, R2 undefined
;    
;   Assumptions:    1) MMU and data cache are enabled prior to this code.
;                   2) lineCount is 1 .. 1024.  Not checked.
;                   3) Region is aligned on a 32-byte boundary.
;                   4) Region size is 32 bytes * lineCount.  Not checked.
;

    ALIGN
    EXPORT  XsLockDataIntoCache
XsLockDataIntoCache

    MOV R2, R0                      ; Protect line count: CPWAIT uses R0

    ; Wait for all pending external data operations to complete
    DrainBuffersM  R0               ; MCR p15, 0, R0, c7, c10, 4

    ; Put the data cache in lock mode
    EnableDCacheLockModeM   R0      ;  MCR P15,0,R0,C9,C2,0: R0=1 
    CPWAIT                          ; Wait for CP15 setting activation; uses R0

    ALIGN
LockDataIntoCacheLoop  ; Loop top 

    ; Next two operations permit locking data that are already in the cache.
    ;  If data from the target address are not in the cache, they become no-ops.

    ; Write back the line if it抯 dirty in the cache 
    InvalidateDCacheLineM  R1       ; (MCR P15,0,R1,C7,C10,1)
    ; Invalidate the line from the cache 
    InvalidateDCacheLineM  R1       ; (MCR P15,0,R1, C7,C6,1)

    ; Load and lock 32 bytes of data located at [R1] into the data 
    ; cache. Post-increment the address in R1 to the next cache line.
    PLD  [r1,#32] 

    ; Wait for all pending external data operations to complete
    DrainBuffersM  R0               ; MCR p15, 0, R0, c7, c10, 4

    SUBS R2, R2, #1                 ; Decrement loop count

    BNE LockDataIntoCacheLoop       ; Back to loop top if nonzero

    ; Turn off data cache locking
    DrainBuffersM  R0
    
    ; Take the data cache out of lock mode. 
    DisableDCacheLockModeM  R0      ; MCR P15,0,R0,C9,C2,0: R0=0 

    CPWAIT

	MOV     pc,lr                   ; return

; End XsLockDataIntoCache()

;----------------------------
; void XsCreateDataRAM  (UINT32 lineCount, UINT32 regionBaseAddr)
;
;   Create a Data RAM
;   Based on the code example in the Intel XScale Core user's manual.
;
;   What is data RAM?  (From the Cotulla OS developer's guide)
;       There are two distinct ways to lock data in the data cache.
;       The first, called data locking, requires that the virtual 
;       addresses be backed by physical memory.  The second, called 
;       data RAM, allows the definition of a virtual address range 
;       that is not backed by physical memory.  While locked data 
;       may be either write back or write through, data RAM must 
;       be write back.
;
;   Input:          R0:  The number of 32-byte lines to designate as 
;                           data RAM (Must be 1 .. 1024. Not checked.)
;                   R1:  The virtual address of a region of memory
;                           to configure as data RAM

;   Return:         None
;
;   Side Effects:   R0, R1, R2, R3 undefined
;    
;   Assumptions:    1) MMU and data cache are enabled prior to this code.
;                   2) lineCount is 1 .. 1024.  Not checked.
;                   3) MMU is configured so that the memory region is 
;                       cacheable.
;                   4) Memory region is aligned on a 32-byte boundary.
;                   5) Region size is 32 bytes * lineCount.  Not checked.
;

    ALIGN
    EXPORT  XsCreateDataRAM
XsCreateDataRAM

    ; Macro uses R4, so R4 must be saved on the stack and restored
    ; for ARM compiler conventions

    STMDB    R13!,{R4,R14}          ; Push R4 and return address on stack

    STR R4, [SP,#-4]

    MOV R4, R0                      ; Protect line count: CPWAIT uses R0

    ; Wait for all pending external data operations to complete
    DrainBuffersM  R0               ; MCR p15, 0, R0, c7, c10, 4

    ; Set to zero the two registers whose values will be used to initialize
    ; the allocated lines.  The STRD instruction uses two sequential 
    ; registers, starting with an even register: here R2+R3
    MOV R2, #0x0
    MOV R3, #0x0

    ; Put the data cache in lock mode
    EnableDCacheLockModeM   R0      ;  MCR P15,0,R0,C9,C2,0: R0=1 
    CPWAIT                          ; Wait for CP15 setting activation; uses R0

    ALIGN
CreateDataRAMLoop  ; Loop top Local macro label per ARM assembler conventions

    ; Allocate and lock a tag into the data cache at address [R1]
    AllocateDCacheLineM R1  ; MCR p15, 0, R1, c7, c2, 5

    ; initialize 32 bytes of newly allocated line
    ; Wait for all pending external data operations to complete
    DrainBuffersM  R0               ; MCR p15, 0, R0, c7, c10, 4
    STRD R2, [R1],#8 ;
    STRD R2, [R1],#8 ;
    STRD R2, [R1],#8 ;
    STRD R2, [R1],#8 ;
    SUBS R4, R4,  #1 ; Decrement loop count
    BNE CreateDataRAMLoop           ; Back to loop top if nonzero

    ; Turn off data cache locking
    ; Wait for all pending external data operations to complete
    DrainBuffersM  R0               ; MCR p15, 0, R0, c7, c10, 4
    ; Take the data cache out of lock mode. 
    DisableDCacheLockModeM  R0      ; MCR P15,0,R0,C9,C2,0: R0=0 

    CPWAIT

	LDMIA    R13!,{R4,PC}           ; Pop R4 and return

; End XsCreateDataRAM()

    END