xscp15.s

pxa27x下rtc程序

XsEnableDCacheLockMode
    EnableDCacheLockModeM r0
    MOV	    pc,lr


;----------------------------
; void XsDisableDCacheLockMode (void)
;
;   End Data cache lock mode enable by writing a "0" to the 
;   Data Cache Lock Register.  Fills to the data cache are
;   not locked in after this command.
;
;   Input:   None
;   Return:  R0 = 0
;    
;   CP 15, CR9, opcode_2=0, CRm2, Contents of Rd=0.
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c2, 0

    ALIGN
    EXPORT  XsDisableDCacheLockMode
XsDisableDCacheLockMode
    DisableDCacheLockModeM r0
    MOV	    pc,lr


;----------------------------
; void XsUnlockInstructionCache (void)
;
;   Unlock the entire the Instruction Cache.
;       Note: There is no way to unlock a subset of the ICache.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR9, opcode_2=1, CRm1
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c1, 1

    ALIGN
    EXPORT  XsUnlockInstructionCache
XsUnlockInstructionCache
    UnlockInstructionCacheM r0
    MOV	    pc,lr


;----------------------------
; void XsUnlockDataCache (void)
;
;   Unlock the entire Data Cache
;       Note: There is no way to unlock a subset of the DCache.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR9, opcode_2=1, CRm2
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c2, 1

    ALIGN
    EXPORT  XsUnlockDataCache
XsUnlockDataCache
    UnlockDataCacheM r0
    MOV	    pc,lr


;=========================================================================
; TLB (Translation Lookaside Buffer) Lock Down.   CP15, CR10.  
;
;   - Write only.
;
;   Notes: This is an MMU-related register
;          Lock/unlock operations when MMU is disabled have an undefined effect.
;          For applicable protocols, see the Memory Management section of the 
;            Intel XScale Core user's manual
;
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
; 
;   Translate and Lock I TLB entry    0b000 0b0100 MVA        MCR p15, 0, Rd, c10, c4, 0
;   Translate and Lock D TLB entry    0b000 0b1000 MVA        MCR p15, 0, Rd, c10, c8, 0
;   Unlock I TLB                      0b001 0b0100 Ignored    MCR p15, 0, Rd, c10, c4, 1
;   Unlock D TLB                      0b001 0b1000 Ignored    MCR p15, 0, Rd, c10, c8, 1
; 


;----------------------------
; void XsTranslateAndLockITLB_Entry (UINT32 MVA)
;
;   Translate an MVA to its physical address and lock it into the 
;       Instruction TLB.
;   - Avoids the overhead of TLB misses when executing instructions 
;       from this address in the future.
;
;   Input:   R0: Will contain the MVA to be translated and 
;                  locked in the ITLB.
;   Return:  None
;    
;   CP 15, CR10, opcode_2=0, CRm4
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c4, 0

    ALIGN
    EXPORT  XsTranslateAndLockITLB_Entry
XsTranslateAndLockITLB_Entry
    TransAndLockITLB_EntryM r0
    MOV	    pc,lr


;----------------------------
; void XsTransAndLockDTLB_Entry (UINT32 MVA)
;
;   Translate an MVA to its physical address and lock it into the 
;       Data TLB.
;   - Avoids the overhead of TLB misses when accessing data 
;       at this address in the future.
;
;   Input:   R0: Will contain MVA to be translated and 
;                           locked in the DTLB.
;   Return:  None
;    
;   CP 15, CR10, opcode_2=0, CRm8
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c8, 0

    ALIGN
    EXPORT  XsTransAndLockDTLB_Entry
XsTransAndLockDTLB_Entry
    TransAndLockDTLB_EntryM r0
    MOV	    pc,lr


;----------------------------
; void XsUnlockInstructionTLB (void)
;
;   Unlock the entire Instruction Translation Lookaside Buffer.
;       Note: There is no way to unlock a subset of the ITLB.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR10, opcode_2=1, CRm4
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c4, 1

    ALIGN
    EXPORT  XsUnlockInstructionTLB
XsUnlockInstructionTLB
    UnlockInstructionTLBM r0
    MOV	pc,lr


;----------------------------
; void XsUnlockDataTLB (void)
;
;   Unlock the entire Data Translation Lookaside Buffer.
;       Note: There is no way to unlock a subset of the DTLB.
;
;   Input:   None
;   Return:       None
;    
;   CP 15, CR10, opcode_2=1, CRm8
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c10, c8, 1

    ALIGN
    EXPORT  XsUnlockDataTLB
XsUnlockDataTLB
    UnlockDataTLBM r0
    MOV	    pc,lr


;=========================================================================
;
; Note: CP15's CR11 and CR12 are reserved.
;


;=========================================================================
;  Process ID (PID)  CP15, CR13, no opcode_2 
;
;  Note: This is an MMU-related register
;         
;

;----------------------------
; UINT32 XsGetProcessID (void)
;
;   Get value of the Process ID (PID) Register.
;
;   Input:   None
;   Return:  R0 contains existing value (as found in register, not 
;            right-shifted).
;
;   CP 15, reg 13
;   MCR/MRC CP15, 0, Rd, c13, c0, 0
;   Nonsymbolic core instruction: 
;       MRC CP15, 0, Rd, c13, c0, 0

    ALIGN
    EXPORT  XsGetProcessID
XsGetProcessID
    GetProcessIDM r0
    MOV	pc,lr

;----------------------------
; void XsSetProcessID (UINT32 PID addr)
;
;   Set value of the Process ID (PID) Register.
; 
;   Input:  R0 contains new value.   Must be as it will be placed in the 
;           register - only values that are even multiples of 0x02000000.
;           A value of zero effectively disables the effect on virtual
;           addresses.
;   Return: None
;    
;   CP 15, reg 13
;   MCR/MRC CP15, 0, Rd, c13, c0, 0
;   Nonsymbolic core instruction: 
;      MCR CP15, 0, Rd, c13, c0, 0

    ALIGN
    EXPORT  XsSetProcessID
XsSetProcessID
    SetProcessIDM r0
    MOV	    pc,lr


;=========================================================================
; Breakpoint Registers  CP15, CR14, opcode_2 varies
;
;   Not implemented.
;
;   Note: It is unclear that subroutines for this purpose would be useful.
;


;=========================================================================
;  Coprocessor Access Register  CP15, CR15, opcode_2 = 0, CRm=1
;
;  - Read/Write
;

;----------------------------
; UINT32 XsGetCoprocessorAccess (void)
;
;   Get value of the Coprocessor Access Register.
; 
;   Input:   None
;   Return:  R0 contains existing value
;
;   CP 15, reg 15, opcode_2 = 0, CRm=1
;   Nonsymbolic core instruction: 
;       MRC CP15, 0, Rd, c15, c1, 0

    ALIGN
    EXPORT  XsGetCoprocessorAccess
XsGetCoprocessorAccess
    GetCoprocessorAccessM r0
    MOV	    pc,lr


;----------------------------
; void XsSetCoprocessorAccess (UINT32)
;
;   Set value of the Coprocessor Access Register.
; 
;   Input:   R0 contains new value
;   Return:  None
;    
;   CP 15, reg 15, opcode_2 = 0, CRm=1
;   Nonsymbolic core instruction: 
;       MCR CP15, 0, Rd, c15, c1, 0

    ALIGN
    EXPORT  XsSetCoprocessorAccess
XsSetCoprocessorAccess
    SetCoprocessorAccessM r0
    MOV	pc,lr


;----------------------------
; void XsInvalidateAllCaches (void)
;
;   Invalidate both the Instruction and Data caches, 
;       plus the Branch Target Buffer, plus both Translation
;       Lookaside Buffers.  Then wait for the coprocessor to finish.
;
;   Input:        None
;   Return:       None
;    
;   Nonsymbolic core instructions: 
;       MCR p15, 0, Rd, c7, c7, 0
;       MCR p15, 0, Rd, c8, c7, 0

    ALIGN
    EXPORT  XsInvalidateAllCaches
XsInvalidateAllCaches
    InvalidIAndDCachesAndBTBM r0
    InvalidateBTBM r0
    CPWAIT
	MOV     pc,lr

; End XsInvalidateAllCaches ()

    ; Force accumulated code-oriented data to be written here.
    ; If there are problems, this may have to be performed
    ;   earlier in this file, also.
	LTORG 


;=========================================================================
; void XsCleanDCache (void)
;
;   Two implementations of cleaning the data cache.
;
;   The faster implementation requires that a 32K virtual memory region 
;   with cacheable MMU attributes be reserved for cleaning the general
;   data cache.  To clean the Mini-data Cache, it also requires a 
;   separate 2K data region with Mini-data Cache attributes.  If the 
;   Mini-data Cache is not used in the system, any valid memory region
;   of 2K is acceptable in its place.
;
;   The slower implementation does not assume that any memory region is
;   reserved for the cache cleaning operation.  It does need a 64Kk 
;   virtual memory region with cacheable MMU attributes and a 4K region
;   that has Mini-data Cache attributes.  If the Mini-data Cache is not
;   used in the system, any valid memory region of 4K is acceptable in 
;   its place.
;


    IF :DEF: DEDICATED_CACHE_CLEANING_MEM
    ; Yes, memory blocks are dedicated to cleaning the data caches

;----------------------------
; void XsCleanDCache (UINT32 dcacheBufP, UINT32 miniDCacheBufP) 
; ; fast version
;
;   Global Clean/Invalidate THE DATA CACHE,
;       using the fastest possible method.
;
;   Assumes that there are cacheable memory regions reserved for
;   the cache cleaning operations.
;
;   Slight modification of the example presented in the Intel 
;   XScale Core user's manual (R0 and R1 both contain addresses).
;
;   Input: 
;       R0: Contains the virtual address of a 32K region of cacheable
;           virtual memory reserved for cleaning the normal Data Cache.
;           This region does not need to be backed by physical memory.
;       R1: Contains the virtual address of a 2K region of cacheable
;           memory reserved for cleaning the Mini-data Cache.
;           This region needs to be backed by physical memory.
;           If the Mini-data Cache is not used in the system, any 2K 
;           block of virtual memory may be used so long as it is  
;           backed by physical memory.
;
;   Return:       None
;   Side Effect:  R0, R1, R2 undefined
;
    ALIGN
    EXPORT  XsCleanDCache
XsCleanDCache

    MOV R2, #1024
CleanDCacheLoop1
    ; Allocate a line at the virtual address specified by R0.
    AllocateDCacheLineM R0  ; MCR p15, 0, R0, c7, c2, 5
    ADD R0, R0, #32 ; Increment the address in R0 to the next cache line
    SUBS R2, R2, #1 ; Decrement loop count
    BNE CleanDCacheLoop1       ; Back to loop 1 top if nonzero
    ;
    ;   Clean the Mini-data Cache
    ;   Can抰 use line-allocate command, so cycle 2KB of unused data through.
    ;   R1 contains the virtual address of a region of cacheable memory 
    ;       reserved for cleaning the Mini-data Cache
    ;   R2 is the loop count. Iterate 64 times which is the number of 
    ;       lines in the Mini-data Cache.