xscp15.s

pxa27x下rtc程序

    InvalidIAndDCachesAndBTBM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateICacheAndBTB (void)
;
;   Invalidate the Instruction cache, plus the Branch Target Buffer.
;   - Individual cache lines can be invalidated using other commands.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR7, opcode_2=0, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, R0, c7, c5, 0

    ALIGN
    EXPORT  XsInvalidateICacheAndBTB
XsInvalidateICacheAndBTB
    InvalidateICacheAndBTBM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateDCache (void)
;
;   Invalidate the Data cache
;   - Individual cache lines can be invalidated using other commands.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR7, opcode_2=0, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c6, 0

    ALIGN
    EXPORT  XsInvalidateDCache
XsInvalidateDCache
    InvalidateDCacheM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateICacheLine (UINT32)
;
;   Invalidate a line in the Instruction cache.
;   - Does not invalidate the BTB.
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   R0: MVA identifying the Instruction cache line to be invalidated
;   Return:  None
;    
;   CP 15, CR7, opcode_2=1, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c5, 1

    ALIGN
    EXPORT  XsInvalidateICacheLine
XsInvalidateICacheLine
    InvalidateICacheLineM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateDCacheLine (UINT32)
;
;   Invalidate a line in the Data cache
;
;    Note: A sequence of calls to this function should be followed by 
;           a call to CpWait() to guarantee activation of the desired
;           state before proceeding. 
;         See the Invalidate Operation section of the 
;           Intel XScale Core user's manual for notes concerning
;           the use of this operation.
;     
;    Input:   R0: Will contain MVA identifying the 
;                        Data cache line to be invalidated
;    Return:  None
;
;    CP 15, CR7, opcode_2=1, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c6, 1

    ALIGN
    EXPORT  XsInvalidateDCacheLine
XsInvalidateDCacheLine
    InvalidateDCacheLineM r0
    MOV	    pc,lr


;----------------------------
; void XsCleanDCacheLine (UINT32 MVA)
;
;   Clean a line in the Data cache
;
;   - Updates external memory with data from the "dirty" portions of 
;       a specific line in data cache and clears the dirty bits.
;   - Leaves line marked as clean but still valid.
;
;   Input:   R0: MVA identifying the Data cache line to be cleaned
;   Return:  None
;    
;   CP 15, CR7, opcode_2=1, CRm10
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c10, 1

    ALIGN
    EXPORT  XsCleanDCacheLine
XsCleanDCacheLine
    CleanDCacheLineM r0
    MOV	    pc,lr


;----------------------------
; void XsDrainBuffers (void)
;
;   Drain the write and fill buffers of the cache.
;
;   - Guarantees that before the next instruction executes, 
;     core data requests to external memory have completed.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR7, opcode_2=4, CRm10
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c10, 4

    ALIGN
    EXPORT  XsDrainBuffers
XsDrainBuffers
    DrainBuffersM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateBTB (void)
;
;   Invalidate the Branch Target Buffer.
;   - Needed after invalidating individual instruction cache lines.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR7, opcode_2=6, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c5, 6

    ALIGN
    EXPORT  XsInvalidateBTB
XsInvalidateBTB
    InvalidateBTBM r0
    MOV	    pc,lr

;----------------------------
;  void XsAllocateDCacheLine(UINT32 mVA)
;
;   Allocate a line in the Data cache
;
;   - Allocates a tag into the data cache specified by 
;     bits [31:5] of R0.  If a valid dirty line (with a different 
;     MVA) already exists at this location it will be evicted.
;
;   WARNING: This command has limited uses and many conditions of
;            safe use.  See the Cache Functions section and Data Cache 
;            section of the Core user's guide for details.
;
;   Input:   R0 bits[31:5]: MVA identifying the Data cache tag to be allocated.
;   Return:  None
;    
;   CP 15, CR7, opcode_2=5, CRm2
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c7, c2, 5

    ALIGN
    EXPORT  XsAllocateDCacheLine
XsAllocateDCacheLine
    AllocateDCacheLineM r0 
    MOV	    pc,lr


;=========================================================================
;  TLB (Translation Lookaside Buffer) operations.   CP15, CR8.  Write only.
;
;  Notes:   This is an MMU-related register
;			Invalidating a TLB entry or the entire TLB does not unlock it.
;           
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
;
;   Invalidate I&D TLB              0b000 0b0111 Ignored MCR p15, 0, Rd, c8, c7, 0
;   Invalidate I TLB                0b000 0b0101 Ignored MCR p15, 0, Rd, c8, c5, 0
;   Invalidate I TLB entry          0b001 0b0101 MVA     MCR p15, 0, Rd, c8, c5, 1
;   Invalidate D TLB                0b000 0b0110 Ignored MCR p15, 0, Rd, c8, c6, 0
;   Invalidate D TLB entry          0b001 0b0110 MVA     MCR p15, 0, Rd, c8, c6, 1
; 

;----------------------------
;  void XsInvalidateIandDTLBs (void)
;
;   Invalidate both the Instruction and Data TLBs
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - Individual TLB entries may be invalidated by using other commands to CP15.
;
;   Input:   None
;   Return:  None
;    
;   CP 15, CR8, opcode_2=0, CRm7
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c7, 0

    ALIGN
    EXPORT  XsInvalidateIandDTLBs
XsInvalidateIandDTLBs
    InvalidateIandDTLBsM r0
    MOV	    pc,lr

;----------------------------
; void XsInvalidateITLB (void)
;
;   Invalidate the Instruction TLB
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - Individual TLB entries may be invalidated by using other commands to CP15.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR8, opcode_2=0, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c5, 0

    ALIGN
    EXPORT  XsInvalidateITLB
XsInvalidateITLB
    InvalidateITLBM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateDTLB (void)
;
;   Invalidate the Data TLB
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - Individual TLB entries may be invalidated by using other commands to CP15.
;
;   Input:         None
;   Return:        None
;    
;   CP 15, CR8, opcode_2=0, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c6, 0

    ALIGN
    EXPORT  XsInvalidateDTLB
XsInvalidateDTLB
    InvalidateDTLBM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateITLBEntry (UINT32 MVA)
;
;   Invalidate an Instruction TLB Entry
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   R0: Will contain MVA identifying the 
;                  Instruction TLB entry to be invalidated
;   Return:  None
;    
;   CP 15, CR8, opcode_2=1, CRm5
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c5, 1

    ALIGN
    EXPORT  XsInvalidateITLBEntry
XsInvalidateITLBEntry
    InvalidateITLBEntryM r0
    MOV	    pc,lr


;----------------------------
; void XsInvalidateDTLBEntry (UINT32 MVA)
;
;   Invalidate a Data TLB Entry
;   - When memory is remapped, all TLB entries relating to the old mapping must be
;       invalidated.
;   - See the Invalidate Operation section of the 
;       Intel XScale Core user's manual for notes concerning
;       the use of this operation.
;
;   Input:   R0: Will contain MVA identifying the 
;                  Data TLB entry to be invalidated
;   Return:  None
;    
;   CP 15, CR8, opcode_2=1, CRm6
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c8, c6, 1

    ALIGN
    EXPORT  XsInvalidateDTLBEntry
XsInvalidateDTLBEntry
    InvalidateDTLBEntryM r0
    MOV	    pc,lr


;=========================================================================
; Cache Lock Down.   CP15, CR9.  Write only.
;
;   Notes: This is an MMU-related register
;          Lock/unlock operations on a disabled cache have an undefined effect.
;
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
; 
;   Fetch and Lock I cache line     0b000 0b0001 MVA        MCR p15, 0, Rd, c9, c1, 0
;   Write data cache lock           0b000 0b0010 Set/Clear  MCR p15, 0, Rd, c9, c2, 0
;         register                                 lock mode 
;   Unlock Instruction cache        0b001 0b0001 Ignored    MCR p15, 0, Rd, c9, c1, 1
;   Unlock Data Cache               0b001 0b0010 Ignored    MCR p15, 0, Rd, c9, c2, 1
; 

;----------------------------
; void XsFetchAndLockICacheLine (UINT32 MVA)
;
;   Fetch and lock an instruction cache line from the specified MVA
;   - Avoids the overhead of cache misses when executing instructions 
;       from this address in the future.
;
;   Input:   R0 contains target MVA
;   Return:  None
;    
;   CP 15, CR9, opcode_2=0, CRm1
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c1, 0

    ALIGN
    EXPORT  XsFetchAndLockICacheLine
XsFetchAndLockICacheLine
    FetchAndLockICacheLineM r0
    MOV	    pc,lr


;----------------------------
; void XsEnableDCacheLockMode (void)
;
;   Begin Data cache lock mode enable by writing a "1" to the 
;   Data Cache Lock Register.  Any fill into the data cache 
;   during this mode gets locked in.
;
;   Notes: 
;     - This is the only way to lock data into the D cache.
;     - Before locking, the programmer must ensure that no part of 
;       the target data range is already resident in the cache. 
;       The Intel XScale core will not refetch such data, which 
;       will result in it not being locked into the cache.
;   
;
;   Input:        None
;   Return:       None
;   Side Effect:  R0 = 1
;    
;   CP 15, CR9, opcode_2=0, CRm2, Contents of Rd=1.
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, c9, c2, 0

    ALIGN
    EXPORT  XsEnableDCacheLockMode