xscp15.s

pxa27x下rtc程序

;----------------------------------------------------------------------
;   Copyright (C) 2000 Intel Corp.
;
;   Filename XsCp15.s
;
;   This file contains Intel(R) Xscale(TM) Microarchitecture 
;       Coprocessor 15 handling functions.
;
;   - Includes MMU functions
;   - These functions are implemented using macros defined in XsCp15.inc
;   - These functions follow the parameter passing conventions specified
;       for the ARM ADS 1.01 C compiler.
;   - For function list, see XsCp15.h
;
; Note: The subroutines in this file follow the ARM ADS 1.01 C language 
;       procedure call standard.  This implies that registers R0..R3 
;       are not restored before returning.  R0 is used for those 
;       subroutines that return an integer value. 
;
;    2000-01-22

    INCLUDE XsCp.inc
    INCLUDE XsCp15.inc


    KEEP
    
    AREA XsCp, ALIGN=5, CODE

;=========================================================================
; void XsCpWait (void)
;
;   Standard function to let CP15 commands complete before moving to
;   next operation.  Uses CPWAIT macro taken from Intel XScale 
;   Core user's manual.
;
;   Input:         None
;   Return:        None
;   Side Effects:  R0 undefined
;   
;
;;  The following function should be used when software needs to be
;;  assured that a CP15 update has taken effect.
;;  It may only be used while in a privileged mode, because it
;;  accesses CP15.

    ALIGN
    EXPORT  XsCpWait
XsCpWait
    CPWAIT
    MOV	    pc,lr


;=========================================================================
; ID & Cache Type
;
;   CP15, CR0, opcod_2=0,1
;
;   Read-only
;

;----------------------------
; UINT32 XsGetProcessorVersion (void)
;
;   Get processor version info
;
;   Input:   None
;   Return:  R0:  ID Register contents
;
;   Note: For first silicon of Cotulla, should be 0x69052000
;
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 0, 0, 0

    ALIGN
    EXPORT  XsGetProcessorVersion
XsGetProcessorVersion
    GetProcVersionM r0
    MOV	    pc,lr

;----------------------------
; UINT32 XsGetCacheType (void)
;
;   Get cache type info 
;
;   Input:   None
;   Return:  R0:  ID Register contents
;
;   CP 15, reg 0, opcode_2=1
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 0, 0, 1

    ALIGN
    EXPORT  XsGetCacheType
XsGetCacheType
    GetCacheTypeM r0
    MOV	    pc,lr

;=========================================================================
;  Control & Auxiliary Control
;
;   CP15, CR1, opcod_2=0,1
;
;   Read/Write
;


;----------------------------
; UINT32 XsGetARMControl (void)
;
;   Get the value in the ARM Control Register.
;
;   Input:   None
;   Return:  R0:  ARM Control Register contents
;
;   CP 15, reg 1, opcode_2=0
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 0, 0, 1

    ALIGN
    EXPORT  XsGetARMControl
XsGetARMControl
    GetARMControlM r0
    MOV	    pc,lr


;----------------------------
; void XsSetARMControl (UINT32)
;
;   Set the value of the ARM Control Register.
;
;   Input:   R0:  New ARM Control Register contents
;   Return:  None
;
;   CP 15, reg 1, opcode_2=0
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, 1, 0, 0

    ALIGN
    EXPORT  XsSetARMControl
XsSetARMControl
    SetARMControlM r0
    MOV	    pc,lr


;----------------------------
; UINT32 XsGetAuxControl (void)
;
;   Get the value in the Auxiliary Control Register.
;
;   Input:   None
;   Return:  R0:  Auxiliary Control Register contents
;
;   CP 15, reg 1, opcode_2=1
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 1, 0, 1

    ALIGN
    EXPORT  XsGetAuxControl
XsGetAuxControl
    GetAuxControlM r0
    MOV	    pc,lr


;----------------------------
; void XsSetAuxControl (UINT32)
;
;
;   Set the value in the Auxiliary Control Register.
;
;   Input:   R0:  New Auxiliary Control Register contents
;   Return:  None
;
;   CP 15, reg 1, opcode_2=1
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, 1, 0, 1

    ALIGN
    EXPORT  XsSetAuxControl
XsSetAuxControl
    SetAuxControlM r0
    MOV	    pc,lr


;=========================================================================
;  Translation Table Base   CP15, CR2
;
;  Note: This is an MMU-related register
;
;  Read/Write
;

;----------------------------
; UINT32 XsGetTransTableBase (void)
;
;   Get physical address of the base of the first-level translation
;       table as known to the MMU. Sometimes called "page table"
;
;   Input:   None
;   Return:  R0:  Translation Table Base Register contents
;
;   CP 15, reg 2
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 2, 0, 0

    ALIGN
    EXPORT  XsGetTransTableBase
XsGetTransTableBase
    GetTransTableBaseM r0

    MOV	    pc,lr


;----------------------------
;
; void XsSetTransTableBase (UINT32)
;
;   Put physical address of the base of the first-level translation
;       table into the Translation Table Base Register so that the 
;       MMU sees it.  Sometimes called "page table" base.
;
;   Input:   R0:  Translation Table base physical address
;   Return:  None
;
;   CP 15, reg 2
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, 2, 0, 0

    ALIGN
    EXPORT  XsSetTransTableBase
XsSetTransTableBase
    SetTransTableBaseM r0
    MOV	    pc,lr


;=========================================================================
;  Domain Access Control   CP15, CR3
;
;  Note: This is an MMU-related register
;
;  Read/Write
;


;----------------------------
; UINT32 XsGetDomainAccessControl (void)
;
;   Get value of the Domain Access Control Register.
;
;   Input:   None
;   Return:  R0: Domain Access Control Register contents
;
;   CP 15, reg 3
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 3, 0, ss0

    ALIGN
    EXPORT  XsGetDomainAccessControl
XsGetDomainAccessControl
    GetDomainAccessControlM r0
    MOV	    pc,lr


;----------------------------
; void XsSetDomainAccessControl (UINT32)
;
;   Set value of the Domain Access Control Register.
;
;   Input:   R0: New Domain Access Control Register contents
;   Return:  None
;
;   Note: No protection against placing the 0b10 Reserved value in
;           any of the individual domain access control fields.
;
;   CP 15, reg 3
;   Nonsymbolic core instruction: 
;       MCR p15, 0, Rd, 3, 0, 0

    ALIGN
    EXPORT  XsSetDomainAccessControl
XsSetDomainAccessControl
    SetDomainAccessControlM r0
    MOV	    pc,lr



;=========================================================================
;
; Note: CP15 CR4 is reserved.
;


;=========================================================================
;  Fault Status and Address   CP15, CR5 and CR6.  
;
;  - Read only.
;

;----------------------------
; UINT32 XsGetFaultStatus (void)
;
;   Get value of the Fault Status Register.
;
;   Input:   None
;   Return:  R0: Fault Status Register contents
;
;   CP 15, reg 5
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 5, 0, 0

    ALIGN
    EXPORT  XsGetFaultStatus
XsGetFaultStatus
    GetFaultStatusM r0
    MOV	    pc,lr


;----------------------------
; UINT32 XsGetFaultAddress (void)
;
;   Get value of the Fault Address Register.
;
;   Input:   None
;   Return:  R0: Fault Address Register contents
;
;   CP 15, reg 6
;   Nonsymbolic core instruction: 
;       MRC p15, 0, Rd, 6, 0, 0

    ALIGN
    EXPORT  XsGetFaultAddress
XsGetFaultAddress
    GetFaultAddressM r0
    MOV	    pc,lr


;=========================================================================
;  Cache operations.   CP15, CR7.  Write only.
;
;  Notes: This is an MMU-related register
;         Be familiar with warnings, assumptions and usage examples in the  
;           Intel XScale Core user's manual and the specific processor's
;           user's manual.  Especially be aware of the ABSENCE of side 
;           effects.  For example, 
;             - Invalidating a cache or cache line does not unlock it.
;             - Invalidating a single instruction cache line does not 
;               automatically invalidate the Branch Target Buffer, which 
;               must be done separately.
; 
;
;   MVA = Modified Virtual Address (VA after possible ORing in of PID reg)
; 
;   Function                     opcode_2  CRm    Data        Instruction
; 
;   Invalidate I&D cache & BTB      0b000 0b0111 Ignored MCR p15, 0, Rd, c7, c7,  0
;   Invalidate I cache & BTB        0b000 0b0101 Ignored MCR p15, 0, Rd, c7, c5,  0
;   Invalidate I cache line         0b001 0b0101 MVA     MCR p15, 0, Rd, c7, c5,  1
;   Invalidate D cache              0b000 0b0110 Ignored MCR p15, 0, Rd, c7, c6,  0
;   Invalidate D cache line         0b001 0b0110 MVA     MCR p15, 0, Rd, c7, c6,  1
;   Clean D cache line              0b001 0b1010 MVA     MCR p15, 0, Rd, c7, c10, 1
;   Drain Write (& Fill) Buffer     0b100 0b1010 Ignored MCR p15, 0, Rd, c7, c10, 4
;   Invalidate Branch Target Buffer 0b110 0b0101 Ignored MCR p15, 0, Rd, c7, c5,  6
;   Allocate Line in the Data Cache 0b101 0b0010 MVA     MCR p15, 0, Rd, c7, c2,  5


;----------------------------
; void XsInvalidIAndDCachesAndBTB (void)
;
;   Invalidate both the Instruction and Data caches, 
;       plus the Branch Target Buffer.
;   - Individual cache lines can be invalidated using other commands.
;
;   Input:        None
;   Return:       None
;    
;   CP 15, CR7, opcode_2=0, CRm7
;   Nonsymbolic core instruction: 
;       MCR p15, 0, R0, c7, c7, 0

    ALIGN
    EXPORT  XsInvalidIAndDCachesAndBTB
XsInvalidIAndDCachesAndBTB