xlli_bulverde_defs.inc

pxa27x下rtc程序

xlli_ICFP_offset        EQU     (0x0C)   ; Interrupt Controller FIQ pending Register
xlli_ICPR_offset        EQU     (0x10)   ; Interrupt Controller Pending Register
xlli_ICCR_offset        EQU     (0x14)   ; Interrupt Controller Control Register
xlli_ICHP_offset        EQU     (0x18)   ; Interrupt Controller Highest Priority Reg
xlli_ICMR2_offset       EQU     (0xA0)   ; Interrupt Controller Mask Register 2
xlli_ICLR2_offset       EQU     (0xA4)   ; Interrupt Controller Level Register 2
xlli_ICCR2_offset       EQU     (0xAC)   ; Interrupt Controller Control Register 2

;
; CLOCK REGISTERS base address and register offsets from the base address
; 

xlli_CLKREGS_PHYSICAL_BASE        EQU     (0x41300000)

xlli_CCCR_offset        EQU     (0x00)  ; Core Clock Configuration Register
xlli_CKEN_offset        EQU     (0x04)  ; Clock-Enable Register
xlli_OSCC_offset        EQU     (0x08)  ; Oscillator Configuration Register
xlli_CCSR_offset        EQU     (0x0C)  ; Core Clock Status Register

xlli_CCCR_A_Bit_Mask    EQU     (0x1 << 25)     ; "A" bit is bit 25 in CCCR
;
; OS TIMER REGISTERS base address and register offsets from the base address
; 

xlli_OSTREGS_PHYSICAL_BASE        EQU     (0x40A00000)

xlli_OSMR0_offset       EQU     (0x00)  ; OS Timer Match Register 0
xlli_OSMR1_offset       EQU     (0x04)  ; OS Timer Match Register 1
xlli_OSMR2_offset       EQU     (0x08)  ; OS Timer Match Register 2
xlli_OSMR3_offset       EQU     (0x0C)  ; OS Timer Match Register 3

xlli_OSCR0_offset       EQU     (0x10)  ; OS Timer Count Register 0
xlli_OSSR_offset        EQU     (0x14)  ; OS Timer Status Register
xlli_OWER_offset        EQU     (0x18)  ; OS Timer Watchdog Enable Register
xlli_OIER_offset        EQU     (0x1C)  ; OS Timer Interrupt Enable Register

xlli_OSCR4_offset       EQU     (0x40)  ; OS Timer Count Register 4
xlli_OSCR5_offset       EQU     (0x44)  ; OS Timer Count Register 5
xlli_OSCR6_offset       EQU     (0x48)  ; OS Timer Count Register 6
xlli_OSCR7_offset       EQU     (0x4C)  ; OS Timer Count Register 7
xlli_OSCR8_offset       EQU     (0x50)  ; OS Timer Count Register 8
xlli_OSCR9_offset       EQU     (0x54)  ; OS Timer Count Register 9
xlli_OSCR10_offset      EQU     (0x58)  ; OS Timer Count Register 10
xlli_OSCR11_offset      EQU     (0x5C)  ; OS Timer Count Register 11

xlli_OSMR4_offset       EQU     (0x80)  ; OS Timer Match Register 4
xlli_OSMR5_offset       EQU     (0x84)  ; OS Timer Match Register 5
xlli_OSMR6_offset       EQU     (0x88)  ; OS Timer Match Register 6
xlli_OSMR7_offset       EQU     (0x8C)  ; OS Timer Match Register 7
xlli_OSMR8_offset       EQU     (0x90)  ; OS Timer Match Register 8
xlli_OSMR9_offset       EQU     (0x94)  ; OS Timer Match Register 9
xlli_OSMR10_offset      EQU     (0x98)  ; OS Timer Match Register 10
xlli_OSMR11_offset      EQU     (0x9C)  ; OS Timer Match Register 11

xlli_OMCR4_offset       EQU     (0xC0)  ; OS Timer Match Control Register 4
xlli_OMCR5_offset       EQU     (0xC4)  ; OS Timer Match Control Register 5
xlli_OMCR6_offset       EQU     (0xC8)  ; OS Timer Match Control Register 6
xlli_OMCR7_offset       EQU     (0xCC)  ; OS Timer Match Control Register 7
xlli_OMCR8_offset       EQU     (0xD0)  ; OS Timer Match Control Register 8
xlli_OMCR9_offset       EQU     (0xD4)  ; OS Timer Match Control Register 9
xlli_OMCR10_offset      EQU     (0xD8)  ; OS Timer Match Control Register 10
xlli_OMCR11_offset      EQU     (0xDC)  ; OS Timer Match Control Register 11

xlli_OSSR_ALL           EQU     (0xFFF) ; Match register status "sticky bits"
xlli_OIER_E1            EQU     (0x002) ; Interrupt enable bit for match register #1

;
; REAL TIME CLOCK (RTC) REGISTERS base address and register offsets from the base address
; 

xlli_RTCREGS_PHYSICAL_BASE      EQU     (0x04090000)

xlli_RCNR_offset        EQU     (0x00)  ; RTC Counter Register
xlli_RTAR_offset        EQU     (0x04)  ; RTC Alarm Register
xlli_RTSR_offset        EQU     (0x08)  ; RTC Status Register
xlli_RTTR_offset        EQU     (0x0C)  ; RTC Timer Trim Register
xlli_RDCR_offset        EQU     (0x10)  ; RTC Day Counter Register
xlli_RYCR_offset        EQU     (0x14)  ; RTC Year Counter Register 
xlli_RDAR1_offset       EQU     (0x18)  ; RTC Day Alarm Register 1
xlli_RYAR1_offset       EQU     (0x1C)  ; RTC Year Alarm Register 2
xlli_RDAR2_offset       EQU     (0x20)  ; RTC Day Alarm Register 2
xlli_RYAR2_offset       EQU     (0x24)  ; RTC Year Alarm Register 2
xlli_SWCR_offset        EQU     (0x28)  ; Stopwatch Counter Register
xlli_SWAR1_offset       EQU     (0x2C)  ; Stopwatch Alarm Register 1
xlli_SWAR2_offset       EQU     (0x30)  ; Stopwatch Alarm Register 2
xlli_PICR_offset        EQU     (0x34)  ; Periodic Interrupt Counter Register
xlli_PIAR_offset        EQU     (0x38)  ; Periodic Interrupt Alarm Register


; Interrupt Controller bit defs

xlli_OSCC_OOK           EQU     (0x01)  ; Oscillator OK bit
xlli_OSCC_OON           EQU     (0x02)  ; Timekeeping (32.768KHz) Osc bit
xlli_OSCC_TOUT_EN       EQU     (0x04)  ; Timekeeping Output enable
xlli_OSCC_PIO_EN        EQU     (0x08)  ; Processor Oscillator Output Enable

;
; Coprocessor 15 data bits
; 

xlli_control_icache  EQU     (0x1000)  ; bit 12 -  i-cache bit
xlli_control_btb     EQU     (0x0800)  ; bit 11 -  btb bit
xlli_control_r       EQU     (0x0200)  ; Bit 9
xlli_control_s       EQU     (0x0100)  ; Bit 8
xlli_control_dcache  EQU     (0x0004)  ; Bit 2  -  d-cache bit
xlli_control_mmu     EQU     (0x0001)  ; Bit 0  -  MMU bit


;
; CP 15 related settings
;

xlli_PID                   EQU     (0x00)
xlli_DACR                  EQU     (0x01)
xlli_CONTROL_DCACHE        EQU     (0x04)
xlli_CONTROL_MINIDATA_01   EQU     (0x10)
xlli_CONTROL_BTB           EQU     (0x800)   ; Brach Target Buffer bit

;
; register bit masks - RCSR
;
xlli_RCSR_HWR         EQU     (0x01)
xlli_RCSR_WDR         EQU     (0x02)
xlli_RCSR_SMR         EQU     (0x04)
xlli_RCSR_GPR         EQU     (0x08)
xlli_RCSR_ALL         EQU     (0xF)


;
;  CPSR Processor constants

xlli_CPSR_Mode_MASK   EQU       (0x0000001F)
xlli_CPSR_Mode_USR    EQU       (0x10)
xlli_CPSR_Mode_FIQ    EQU       (0x11)
xlli_CPSR_Mode_IRQ    EQU       (0x12)
xlli_CPSR_Mode_SVC    EQU       (0x13)
xlli_CPSR_Mode_ABT    EQU       (0x17)
xlli_CPSR_Mode_UND    EQU       (0x1B)
xlli_CPSR_Mode_SYS    EQU       (0x1F)

xlli_CPSR_I_Bit       EQU       (0x80)
xlli_CPSR_F_Bit       EQU       (0x40)


xlli_PWRMODE_SLEEP    EQU       (0x00000003) ; Value for cp14: Reg7 to induce sleep.
;     Bit settings
;
xlli_BIT_0      EQU     0x00000001
xlli_BIT_1      EQU     0x00000002
xlli_BIT_2      EQU     0x00000004
xlli_BIT_3      EQU     0x00000008
xlli_BIT_4      EQU     0x00000010
xlli_BIT_5      EQU     0x00000020
xlli_BIT_6      EQU     0x00000040
xlli_BIT_7      EQU     0x00000080
xlli_BIT_8      EQU     0x00000100
xlli_BIT_9      EQU     0x00000200
xlli_BIT_10     EQU     0x00000400
xlli_BIT_11     EQU     0x00000800
xlli_BIT_12     EQU     0x00001000
xlli_BIT_13     EQU     0x00002000
xlli_BIT_14     EQU     0x00004000
xlli_BIT_15     EQU     0x00008000
xlli_BIT_16     EQU     0x00010000
xlli_BIT_17     EQU     0x00020000
xlli_BIT_18     EQU     0x00040000
xlli_BIT_19     EQU     0x00080000
xlli_BIT_20     EQU     0x00100000
xlli_BIT_21     EQU     0x00200000
xlli_BIT_22     EQU     0x00400000
xlli_BIT_23     EQU     0x00800000
xlli_BIT_24     EQU     0x01000000
xlli_BIT_25     EQU     0x02000000
xlli_BIT_26     EQU     0x04000000
xlli_BIT_27     EQU     0x08000000
xlli_BIT_28     EQU     0x10000000
xlli_BIT_29     EQU     0x20000000
xlli_BIT_30     EQU     0x40000000
xlli_BIT_31     EQU     0x80000000
      END