xlli_bulverde_defs.inc

pxa27x下rtc程序

;*********************************************************************************
;
;        COPYRIGHT (c) 2002 - 2004 Intel Corporation
;
;   The information in this file is furnished for informational use only,
;   is subject to change without notice, and should not be construed as
;   a commitment by Intel Corporation. Intel Corporation assumes no
;   responsibility or liability for any errors or inaccuracies that may appear
;   in this document or any software that may be provided in association with
;   this document.
;
;*********************************************************************************
;
;  FILENAME:       xlli_Bulverde_defs.inc (Core processor address definitions for PXA27x)
;
; LAST MODIFIED:   5-Apr-2004
;
;******************************************************************************
;
; Include file for PXA27x Processor based
; Cross Platform Low Level Initialization  (XLLI)
;

;
; GENERAL PURPOSE I/O (GPIO) base address and register offsets from the base address
;

xlli_GPIOREGS_PHYSICAL_BASE	 EQU 	0x40E00000

; GPIO register offsets from the base address

xlli_GPLR0_offset    EQU    (0x000)  ; GPIO Level registers
xlli_GPLR1_offset    EQU    (0x004)
xlli_GPLR2_offset    EQU    (0x008)
xlli_GPLR3_offset    EQU    (0x100)

xlli_GPDR0_offset    EQU    (0x00C)  ; GPIO Direction registers
xlli_GPDR1_offset    EQU    (0x010)
xlli_GPDR2_offset    EQU    (0x014)
xlli_GPDR3_offset    EQU    (0x10C)

xlli_GPSR0_offset    EQU    (0x018)  ; GPIO Set registers
xlli_GPSR1_offset    EQU    (0x01C)
xlli_GPSR2_offset    EQU    (0x020)
xlli_GPSR3_offset    EQU    (0x118)

xlli_GPCR0_offset    EQU    (0x024)  ; GPIO Clear registers
xlli_GPCR1_offset    EQU    (0x028)
xlli_GPCR2_offset    EQU    (0x02C)
xlli_GPCR3_offset    EQU    (0x124)

xlli_GAFR0_L_offset  EQU    (0x054)  ; GPIO Alternate function registers (Bits 15:0)
xlli_GAFR0_U_offset  EQU    (0x058)  ; Bits 31:16
xlli_GAFR1_L_offset  EQU    (0x05c)  ; Bits 47:32
xlli_GAFR1_U_offset  EQU    (0x060)  ; Bits 63:48
xlli_GAFR2_L_offset  EQU    (0x064)  ; Bits 79:64
xlli_GAFR2_U_offset  EQU    (0x068)  ; Bits 95:80
xlli_GAFR3_L_offset  EQU    (0x06C)  ; Bits 111:96
xlli_GAFR3_U_offset  EQU    (0x070)  ; Bits 127:112

;
; POWER MANAGER base address and register offsets from the base address
;

xlli_PMRCREGS_PHYSICAL_BASE	 EQU 	0x40F00000 

xlli_PMCR_offset        EQU     (0x00)  ; Power Manager Control Register
xlli_PSSR_offset        EQU     (0x04)  ; Power Manager Sleep Status Register
xlli_PSPR_offset        EQU     (0x08)  ; Power Manager Scratch Pad Register
xlli_PWER_offset        EQU     (0x0C)  ; Power Manager Wake-up Enable Register
xlli_PRER_offset        EQU     (0x10)  ; Power Manager GPIO Rising-edge Detect Enable Register
xlli_PFER_offset        EQU     (0x14)  ; Power Manager GPIO Falling-edge Detect Enable Register
xlli_PEDR_offset        EQU     (0x18)  ; Power Manager GPIO Edge Detect Status Register
xlli_PCFR_offset        EQU     (0x1C)  ; Power Manager General Configuration Register
xlli_PGSR0_offset       EQU     (0x20)  ; Power Manager GPIO Sleep State Register for GP [31-0]
xlli_PGSR1_offset       EQU     (0x24)  ; Power Manager GPIO Sleep State Register for GP [63-32]
xlli_PGSR2_offset       EQU     (0x28)  ; Power Manager GPIO Sleep State Register for GP [95-64]
xlli_PGSR3_offset       EQU     (0x2C)  ; Power Manager GPIO Sleep State Register for GP [120-96]
xlli_RCSR_offset        EQU     (0x30)  ; Reset Controller Status Register
xlli_PSLR_offset        EQU     (0x34)  ; Power Manager Sleep Mode Config Register
xlli_PSTR_offset        EQU     (0x38)  ; Power Manager Standby Mode Config Register
xlli_PSNR_offset        EQU     (0x3C)  ; Power Manager Sense Moce Config Register
xlli_PVCR_offset        EQU     (0x40)  ; Power Manager Voltage Change Control Register
xlli_PKWR_offset        EQU     (0x50)  ; Power Manager Keyboard Wake-up Enable Register
xlli_PKSR_offset        EQU     (0x54)  ; Power Manager Keyboard Edge-Detect Status Register
xlli_PI2DBR_offset      EQU     (0x188) ; Power I2C Data Buffer Register
xlli_PI2CR_offset       EQU     (0x190) ; Power I2C Control Register
xlli_PI2SR_offset       EQU     (0x198) ; Power I2C Status Register
xlli_PI2SAR_offset      EQU     (0x1A0) ; Power I2C Slave Address Register

;
; POWER MANAGER register bit masks 
;
xlli_PSSR_SSS           EQU     (0x01)  ; Software Sleep Status
xlli_PSSR_BFS           EQU     (0x02)  ; Battery Fault Status
xlli_PSSR_VFS           EQU     (0x04)  ; VCC Fault Status
xlli_PSSR_PH            EQU     (0x10)  ; Peripheral Control Hold
xlli_PSSR_RDH           EQU     (0x20)  ; Read Disable Hold

xlli_PCFR_OPDE          EQU     (0x01)  ; Processor (13MHz) osc power-down enable
xlli_PCFR_FP            EQU     (0x02)  ; Float PCMCIA during sleep modes
xlli_PCFR_FS            EQU     (0x04)  ; Float Static Chip Selects
xlli_PCFR_SYSEN_EN      EQU     (0x20)  ; SYS_EN pin
xlli_PCFR_DC_EN         EQU     (0x80)  ; Deep-Sleep Mode

xlli_PWER_WE0           EQU     (0x01)          ; Wake-up Enable GPIO pin 0
xlli_PWER_WE1           EQU     (0x02)          ; Wake-up Enable GPIO pin 1
xlli_PWER_WERTC         EQU     (0x80000000)    ; RTC Standby, Wake-up Enable-

;
; MEMORY CONTROLLER base address and register offsets from the base address 
;

xlli_MEMORY_CONFIG_BASE EQU     0x48000000

xlli_MDCNFG_offset      EQU     (0x00)
xlli_MDREFR_offset      EQU     (0x04)
xlli_MSC0_offset        EQU     (0x08)
xlli_MSC1_offset        EQU     (0x0C)
xlli_MSC2_offset        EQU     (0x10)
xlli_MECR_offset        EQU     (0x14)
xlli_SXLCR_offset       EQU     (0x18)
xlli_SXCNFG_offset      EQU     (0x1C)
xlli_FLYCNFG_offset     EQU     (0x20)
xlli_SXMRS_offset       EQU     (0x24)                                       
xlli_MCMEM0_offset      EQU     (0x28)
xlli_MCMEM1_offset      EQU     (0x2C)
xlli_MCATT0_offset      EQU     (0x30)
xlli_MCATT1_offset      EQU     (0x34)
xlli_MCIO0_offset       EQU     (0x38)
xlli_MCIO1_offset       EQU     (0x3C)
xlli_MDMRS_offset       EQU     (0x40)
xlli_BOOT_DEF_offset    EQU     (0x44)
xlli_ARB_CNTL_offset    EQU     (0x48)
xlli_BSCNTR0_offset     EQU     (0x4C)
xlli_BSCNTR1_offset     EQU     (0x50)
xlli_LCDBSCNTR_offset   EQU     (0x54)
xlli_MDMRSLP_offset     EQU     (0x58)
xlli_BSCNTR2_offset     EQU     (0x5C)
xlli_BSCNTR3_offset     EQU     (0x60)

; Memory Controller bit defs

xlli_MDREFR_K0DB4       EQU     (0x20000000)    ; Sync Static Clock 0 divide by 4 control/status
xlli_MDREFR_K2FREE      EQU     (0x02000000)    ; Set to force SDCLK[2] to be free running
xlli_MDREFR_K1FREE      EQU     (0x01000000)    ; Set to force SDCLK[1] to be free running
xlli_MDREFR_K0FREE      EQU     (0x00800000)    ; Set to force SDCLK[0] to be free running
xlli_MDREFR_SLFRSH      EQU     (0x00400000)    ; Self Refresh Control Status bit
xlli_MDREFR_APD         EQU     (0x00100000)    ; Auto Power Down bit
xlli_MDREFR_K2DB2       EQU     (0x00080000)    ; SDRAM clock pin 2 divide by 2 control/status
xlli_MDREFR_K1DB2       EQU     (0x00020000)    ; SDRAM clock pin 1 divide by 2 control/status
xlli_MDREFR_K1RUN       EQU     (0x00010000)    ; SDRAM clock pin 1 run/control status
xlli_MDREFR_E1PIN       EQU     (0x00008000)    ; SDRAM clock Enable pin 1 level control/status
xlli_MDREFR_K0DB2       EQU     (0x00004000)    ; Sync Static Memory Clock divide by 2 control/status
xlli_MDREFR_K0RUN       EQU     (0x00002000)    ; Sync Static Memory Clock Pin 0
xlli_MDREFR_E0PIN       EQU     (0x00000100)    ; SDRAM clock enable pin 0 (Cotulla ONLY!!)

xlli_MDCNFG_DE0         EQU     (0x00000001)    ; SDRAM enable bit for partition 0
xlli_MDCNFG_DE1         EQU     (0x00000002)    ; SDRAM enable bit for partition 1
xlli_MDCNFG_DE2         EQU     (0x00010000)    ; SDRAM enable bit for partition 2
xlli_MDCNFG_DE3         EQU     (0x00020000)    ; SDRAM enable bit for partition 3
xlli_MDCNFG_DWID0       EQU     (0x00000004)    ; SDRAM bus width (clear = 32 bits, set = 16 bits)

;
; INTERNAL MEMORY CONTROLLER base address and register offsets from the base address 
;

xlli_IMEMORY_CONFIG_BASE        EQU     (0x58000000)

xlli_IMPMCR_offset              EQU     (0x00)  ; Internal Memory Power Manager Control Register
xlli_IMPMSR_offset              EQU     (0x08)  ; Internal Memory Power Management Status Register


;
; INTERRUPT CONTROLLER base address and register offsets from the base address
; 

xlli_INTERREGS_PHYSICAL_BASE      EQU     (0x40D00000)

xlli_ICIP_offset        EQU     (0x00)   ; Interrupt Controller IRQ Pending Register
xlli_ICMR_offset        EQU     (0x04)   ; Interrupt Controller Mask Register
xlli_ICLR_offset        EQU     (0x08)   ; Interrupt Controller Level Register