📄 xlli_mainstone_defs.inc
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xlli_MSC0_162 EQU (0x16C016C0)
xlli_MSC0_169 EQU (0x17D017D0) ; Given that the optimal value would be 13 (RDF), but according to B0 manual, it's different
xlli_MSC0_175 EQU (0x17C017C0)
xlli_MSC0_182 EQU (0x17C017C0)
xlli_MSC0_188 EQU (0x17D017D0)
xlli_MSC0_195 EQU (0x17E017E0)
xlli_MSC0_201 EQU (0x18E018E0)
;xlli_MSC0_208 EQU (0x18E018E0)
xlli_MSC0_208 EQU (0x18E02AF0) ;hzh, for test
ENDIF ; xlli_C0_BULVERDE
;
; Optimal values for DTC settings for various MemClk settings (MDCNFG)
;
IF :DEF: xlli_SDRAM_WIDTH_16_BIT
; Really, we should have yet another flag that is dependant on the SDRAM part, but since only
; the MCP's SDRAM parameters are different than the MSII platform, I'm choosing to pick the 16-bit
; width to trigger for the different timing values
xlli_DTC_13 EQU (0x00000000) ; 13 MHz setting
xlli_DTC_19 EQU (0x00000000) ; 19 MHz setting
xlli_DTC_26 EQU (0x00000000) ; 26 MHz setting
xlli_DTC_32 EQU (0x00000000) ; 32 MHz setting
xlli_DTC_39 EQU (0x01000100) ; 39 MHz setting
xlli_DTC_45 EQU (0x01000100) ; 45 MHz setting
xlli_DTC_52 EQU (0x01000100) ; 52 MHz setting
xlli_DTC_58 EQU (0x01000100) ; 58 MHz setting
xlli_DTC_65 EQU (0x01000100) ; 65 MHz setting
xlli_DTC_68 EQU (0x02000200) ; 68 MHz setting
xlli_DTC_71 EQU (0x02000200) ; 71 MHz setting
xlli_DTC_74 EQU (0x02000200) ; 74 MHz setting
xlli_DTC_78 EQU (0x02000200) ; 78 MHz setting
xlli_DTC_81 EQU (0x02000200) ; 81 MHz setting
xlli_DTC_84 EQU (0x02000200) ; 84 MHz setting
xlli_DTC_87 EQU (0x02000200) ; 87 MHz setting
xlli_DTC_91 EQU (0x02000200) ; 91 MHz setting
xlli_DTC_94 EQU (0x02000200) ; 94 MHz setting
xlli_DTC_97 EQU (0x02000200) ; 97 MHz setting
xlli_DTC_100 EQU (0x03000300) ; 100 MHz setting
xlli_DTC_104 EQU (0x03000300) ; 104 MHz setting
xlli_DTC_110 EQU (0x01000100) ; 110 MHz setting - SDCLK Halved
xlli_DTC_117 EQU (0x01000100) ; 117 MHz setting - SDCLK Halved
xlli_DTC_124 EQU (0x01000100) ; 124 MHz setting - SDCLK Halved
xlli_DTC_130 EQU (0x02000200) ; 130 MHz setting - SDCLK Halved
xlli_DTC_136 EQU (0x02000200) ; 136 MHz setting - SDCLK Halved
xlli_DTC_143 EQU (0x02000200) ; 143 MHz setting - SDCLK Halved
xlli_DTC_149 EQU (0x02000200) ; 149 MHz setting - SDCLK Halved
xlli_DTC_156 EQU (0x02000200) ; 156 MHz setting - SDCLK Halved
xlli_DTC_162 EQU (0x02000200) ; 162 MHz setting - SDCLK Halved
xlli_DTC_169 EQU (0x02000200) ; 169 MHz setting - SDCLK Halved
xlli_DTC_175 EQU (0x02000200) ; 175 MHz setting - SDCLK Halved
xlli_DTC_182 EQU (0x02000200) ; 182 MHz setting - SDCLK Halved
xlli_DTC_188 EQU (0x02000200) ; 188 MHz setting - SDCLK Halved
xlli_DTC_195 EQU (0x02000200) ; 195 MHz setting - SDCLK Halved
xlli_DTC_201 EQU (0x03000300) ; 201 MHz setting - SDCLK Halved
xlli_DTC_208 EQU (0x03000300) ; 208 MHz setting - SDCLK Halved
;
; Optimal values for DRI settings for various MemClk settings (MDREFR)
;
xlli_DRI_13 EQU (0x002) ; 13 MHz setting
xlli_DRI_19 EQU (0x003)
xlli_DRI_26 EQU (0x004) ; 26 MHz setting
xlli_DRI_32 EQU (0x006)
xlli_DRI_39 EQU (0x007) ; 39 MHz setting
xlli_DRI_45 EQU (0x009)
xlli_DRI_52 EQU (0x00A) ; 52 MHz setting
xlli_DRI_58 EQU (0x00C)
xlli_DRI_65 EQU (0x00D) ; 65 MHz setting
xlli_DRI_68 EQU (0x00E)
xlli_DRI_71 EQU (0x00F) ; 71 MHz setting
xlli_DRI_74 EQU (0x010)
xlli_DRI_78 EQU (0x010) ; 78 MHz setting
xlli_DRI_81 EQU (0x011)
xlli_DRI_84 EQU (0x012) ; 84 MHz setting
xlli_DRI_87 EQU (0x013)
xlli_DRI_91 EQU (0x013) ; 91 MHz setting
xlli_DRI_94 EQU (0x014) ; 94 MHz setting
xlli_DRI_97 EQU (0x015) ; 97 MHz setting
xlli_DRI_100 EQU (0x016) ; 100 MHz setting
xlli_DRI_104 EQU (0x016) ; 104 MHz setting
xlli_DRI_110 EQU (0x018)
xlli_DRI_117 EQU (0x019) ; 117 MHz setting
xlli_DRI_124 EQU (0x01B)
xlli_DRI_130 EQU (0x01C) ; 130 MHz setting
xlli_DRI_136 EQU (0x01E)
xlli_DRI_143 EQU (0x01F)
xlli_DRI_149 EQU (0x021)
xlli_DRI_156 EQU (0x022)
xlli_DRI_162 EQU (0x024)
xlli_DRI_169 EQU (0x025) ; 169 MHz setting
xlli_DRI_175 EQU (0x027)
xlli_DRI_182 EQU (0x028)
xlli_DRI_188 EQU (0x02A)
xlli_DRI_195 EQU (0x02B)
xlli_DRI_201 EQU (0x02D)
xlli_DRI_208 EQU (0x02E) ; 208 MHz setting
ELSE ; ELSE not 16 bit SDRAM width
xlli_DTC_13 EQU (0x00000000) ; 13 MHz setting
xlli_DTC_19 EQU (0x00000000) ; 19 MHz setting
xlli_DTC_26 EQU (0x00000000) ; 26 MHz setting
xlli_DTC_32 EQU (0x00000000) ; 32 MHz setting
xlli_DTC_39 EQU (0x00000000) ; 39 MHz setting
xlli_DTC_45 EQU (0x00000000) ; 45 MHz setting
xlli_DTC_52 EQU (0x00000000) ; 52 MHz setting
xlli_DTC_58 EQU (0x01000100) ; 58 MHz setting
xlli_DTC_65 EQU (0x01000100) ; 65 MHz setting
xlli_DTC_68 EQU (0x01000100) ; 68 MHz setting
xlli_DTC_71 EQU (0x01000100) ; 71 MHz setting
xlli_DTC_74 EQU (0x01000100) ; 74 MHz setting
xlli_DTC_78 EQU (0x01000100) ; 78 MHz setting
xlli_DTC_81 EQU (0x01000100) ; 81 MHz setting
xlli_DTC_84 EQU (0x01000100) ; 84 MHz setting
xlli_DTC_87 EQU (0x01000100) ; 87 MHz setting
xlli_DTC_91 EQU (0x02000200) ; 91 MHz setting
xlli_DTC_94 EQU (0x02000200) ; 94 MHz setting
xlli_DTC_97 EQU (0x02000200) ; 97 MHz setting
xlli_DTC_100 EQU (0x02000200) ; 100 MHz setting
xlli_DTC_104 EQU (0x02000200) ; 104 MHz setting
xlli_DTC_110 EQU (0x01000100) ; 110 MHz setting - SDCLK Halved
xlli_DTC_117 EQU (0x01000100) ; 117 MHz setting - SDCLK Halved
xlli_DTC_124 EQU (0x01000100) ; 124 MHz setting - SDCLK Halved
xlli_DTC_130 EQU (0x01000100) ; 130 MHz setting - SDCLK Halved
xlli_DTC_136 EQU (0x01000100) ; 136 MHz setting - SDCLK Halved
xlli_DTC_143 EQU (0x01000100) ; 143 MHz setting - SDCLK Halved
xlli_DTC_149 EQU (0x01000100) ; 149 MHz setting - SDCLK Halved
xlli_DTC_156 EQU (0x01000100) ; 156 MHz setting - SDCLK Halved
xlli_DTC_162 EQU (0x01000100) ; 162 MHz setting - SDCLK Halved
xlli_DTC_169 EQU (0x01000100) ; 169 MHz setting - SDCLK Halved
xlli_DTC_175 EQU (0x01000100) ; 175 MHz setting - SDCLK Halved
xlli_DTC_182 EQU (0x02000200) ; 182 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_188 EQU (0x02000200) ; 188 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_195 EQU (0x02000200) ; 195 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_201 EQU (0x02000200) ; 201 MHz setting - SDCLK Halved - Close to edge, so bump up
xlli_DTC_208 EQU (0x02000200) ; 208 MHz setting - SDCLK Halved - Close to edge, so bump up
;
; Optimal values for DRI settings for various MemClk settings (MDREFR)
;
xlli_DRI_13 EQU (0x002) ; 13 MHz setting
xlli_DRI_19 EQU (0x003)
xlli_DRI_26 EQU (0x005) ; 26 MHz setting
xlli_DRI_32 EQU (0x006)
xlli_DRI_39 EQU (0x008) ; 39 MHz setting
xlli_DRI_45 EQU (0x00A)
xlli_DRI_52 EQU (0x00B) ; 52 MHz setting
xlli_DRI_58 EQU (0x00D)
xlli_DRI_65 EQU (0x00E) ; 65 MHz setting
xlli_DRI_68 EQU (0x00F)
xlli_DRI_71 EQU (0x010) ; 71 MHz setting
xlli_DRI_74 EQU (0x011)
xlli_DRI_78 EQU (0x012) ; 78 MHz setting
xlli_DRI_81 EQU (0x012)
xlli_DRI_84 EQU (0x013) ; 84 MHz setting
xlli_DRI_87 EQU (0x014)
xlli_DRI_91 EQU (0x015) ; 91 MHz setting
xlli_DRI_94 EQU (0x016) ; 94 MHz setting
xlli_DRI_97 EQU (0x016) ; 97 MHz setting
xlli_DRI_100 EQU (0x017) ; 100 MHz setting
xlli_DRI_104 EQU (0x018) ; 104 MHz setting
xlli_DRI_110 EQU (0x01A)
xlli_DRI_117 EQU (0x01B) ; 117 MHz setting
xlli_DRI_124 EQU (0x01D)
xlli_DRI_130 EQU (0x01E) ; 130 MHz setting
xlli_DRI_136 EQU (0x020)
xlli_DRI_143 EQU (0x021)
xlli_DRI_149 EQU (0x023)
xlli_DRI_156 EQU (0x025)
xlli_DRI_162 EQU (0x026)
xlli_DRI_169 EQU (0x028) ; 169 MHz setting
xlli_DRI_175 EQU (0x029)
xlli_DRI_182 EQU (0x02B)
xlli_DRI_188 EQU (0x02D)
xlli_DRI_195 EQU (0x02E)
xlli_DRI_201 EQU (0x030)
xlli_DRI_208 EQU (0x031) ; 208 MHz setting
ENDIF ; xlli_SDRAM_WIDTH_16_BIT
;
; SDRAM Settings
;
IF :DEF: xlli_SDRAM_WIDTH_16_BIT
xlli_MDCNFG_value EQU (0x00002BCC) ; SDRAM Config Reg (MCP Version)
ELSE
xlli_MDCNFG_value EQU (0x00000AC8) ; SDRAM Config Reg (Non-MCP Version)
ENDIF
xlli_MDMRS_value EQU (0x00000000) ; SDRAM Mode Reg Set Config Reg
;
; MEMORY PHYSICAL BASE ADDRESS(S)
;
xlli_SRAM_PHYSICAL_BASE EQU (0X5C000000) ; Physical base address for SRAM
xlli_SDRAM_PHYSICAL_BASE EQU (0xA0000000) ; Physical base address for SDRAM
;
; CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone
;
xlli_CCCR_value EQU (0x00000107) ; PXA27x (HW reset value to start)
;
; Clock Enable Register (CKEN) setting
;
xlli_CKEN_value EQU (0x00400200) ; Data to be set into the clock enable register
; bit 9 enables OS timers
; Bit 22 enables memory clock
;
; Address where system configuration data is stored
;
xlli_SCR_data EQU (0x5C03FFFC) ; Address in SRAM where system config data is stored
;
; Misc constants
;
xlli_MemSize_1Mb EQU (0x00100000)
IF :DEF: xlli_SDRAM_SIZE_32_MB
xlli_p_PageTable EQU (0xA1FFC000) ; Base address for memory Page Table (MCP version)
ELSE
xlli_p_PageTable EQU (0xA3FFC000) ; Base address for memory Page Table (Non-MCP version)
ENDIF
xlli_s_PageTable EQU (0x00004000) ; Page Table size (4K words - 16 Kb)
xlli_FLASH_WRITE EQU 0x600060 ; Code for writing to flash
xlli_FLASH_WCONF EQU 0x030003 ; Code to confirm write to flash
xlli_FLASH_READ EQU 0xFF00FF ; Code to place flash in read mode
xlli_FLASH_SYNC_value EQU 0x25C2<<2 ; Value to set flash into sync mode
xlli_SXCNFG_sync_value EQU 0x6011 ; SXCNFG value for sync flash operation
;
; Special conditional required for Power On SelfTest (POST) build
;
IF :DEF: POST_BUILD
xlli_v_xbBOOTROM EQU (0x04000000) ; (0x04000000 for POST)
ELSE
xlli_v_xbBOOTROM EQU (0x00000000)
ENDIF
END
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