📄 xlli_mainstone_defs.inc
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;*********************************************************************************
;
; COPYRIGHT (c) 2002 - 2004 Intel Corporation
;
; The information in this file is furnished for informational use only,
; is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
;
;*********************************************************************************
;
; FILENAME: xlli_Mainstone_defs.inc (Platform specific addresses and
; defalut values for Mainstone II platform bring up)
; NOTE: - This file has a def to configure xlli for MCP and non-MCP processors
;
; LAST MODIFIED: 5-Apr-2004
;
;******************************************************************************
;
;
; Include file for Mainstone II specific Cross Platform Low Level Initialization (XLLI)
;
;xlli_SDRAM_SIZE_32_MB EQU 0 ; Uncomment for 64 Mb of SDRAM
;xlli_SDRAM_WIDTH_16_BIT EQU 0 ; Uncomment as required
;xlli_FLASH_WIDTH_16_BIT EQU 0 ; Uncomment as required
;xlli_C0_BULVERDE EQU 0 ; Uncomment for PXA27x step C0
;
; PLATFORM REGISTERS base address and register offsets from the base address
;
xlli_PLATFORM_REGISTERS EQU 0x08000000
xlli_PLATFORM_HEXLED_DATA_offset EQU (0x10) ; Hex LED Data Register
xlli_PLATFORM_LED_CONTROL_offset EQU (0x40) ; LED Control Register
xlli_PLATFORM_SWITCH_offset EQU (0x60) ; General Purpose Switch Register
xlli_PLATFORM_MISC_WRITE1_offset EQU (0x80) ; Misc Write Register 1
xlli_PLATFORM_MISC_WRITE2_offset EQU (0x84) ; Misc Write Register 2
xlli_PLATFORM_MISC_READ1_offset EQU (0x90) ; Misc Read Register 1
xlli_PLATFORM_INTERR_ME_offset EQU (0xC0) ; Platform Interrupt Mask/Enable Register 1
xlli_PLATFORM_INTERR_SC_offset EQU (0xD0) ; Platform Interrupt Set/Clear Register 1
xlli_PLATFORM_PCMCIA0_SC_offset EQU (0xE0) ; PCMCIA Socket 0 Status/Control Register
xlli_PLATFORM_PCMCIA1_SC_offset EQU (0xE4) ; PCMCIA Socket 1 Status/Control Register
;
; Platform specific bits
;
xlli_SYS_RESET EQU (0x01) ; System reset bit
;
; platform GPIO pin settings (PXA27x/Mainstone)
;
;xlli_GPSR0_value EQU (0x00008004) ; Set registers
;xlli_GPSR1_value EQU (0x00020080)
;xlli_GPSR2_value EQU (0x16C14000)
;xlli_GPSR3_value EQU (0x0003E000)
;xlli_GPCR0_value EQU (0x0) ; Clear registers
;xlli_GPCR1_value EQU (0x00000380) ; FFUART related
;xlli_GPCR2_value EQU (0x0)
;xlli_GPCR3_value EQU (0x0)
xlli_GRER0_value EQU (0x0) ; Rising Edge Detect
xlli_GRER1_value EQU (0x0)
xlli_GRER2_value EQU (0x0)
xlli_GRER3_value EQU (0x0)
xlli_GFER0_value EQU (0x0) ; Falling Edge Detect
xlli_GFER1_value EQU (0x0)
xlli_GFER2_value EQU (0x0)
xlli_GFER3_value EQU (0x0)
xlli_GPLR0_value EQU (0x0) ; Pin Level Registers
xlli_GPLR1_value EQU (0x0)
xlli_GPLR2_value EQU (0x0)
xlli_GPLR3_value EQU (0x0)
xlli_GEDR0_value EQU (0x0) ; Edge Detect Status
xlli_GEDR1_value EQU (0x0)
xlli_GEDR2_value EQU (0x0)
xlli_GEDR3_value EQU (0x0)
;xlli_GPDR0_value EQU (0xCFE3BDE4) ; Direction Registers
;xlli_GPDR1_value EQU (0x003FAB81)
;xlli_GPDR2_value EQU (0x1EC3FC00)
;xlli_GPDR3_value EQU (0x018FFE8F)
;xlli_GAFR0_L_value EQU (0x84400000) ; Alternate function registers
;xlli_GAFR0_U_value EQU (0xA5000510)
;xlli_GAFR1_L_value EQU (0x000A9558)
;xlli_GAFR1_U_value EQU (0x0005A1AA)
;xlli_GAFR2_L_value EQU (0x60000000)
;xlli_GAFR2_U_value EQU (0x00000802)
;xlli_GAFR3_L_value EQU (0x00000000)
;xlli_GAFR3_U_value EQU (0x00000000)
;YL-PXA27x use below, hzh
;0->Input,1->LAN91C111 IRQ,3->LCDPWREN,4->CAMERA PWRDN,
;9->IDE IRQ,10->NAND nCE,11->Buzzer,12->CIF_D7,13->ext.,14->CS8900 IRQ,15->nCS1
;16->LCD BK,17->CIF_D6,18->nWAIT,19->ST16C550 IRQ,20->DREQ,21->DVAL,22->USBD PULL-UP,23->CIF_MCLK
;24->CIF_FV,25->CIF_LV,26->CIF_PCLK,27->CIF_D0,28->AC97_BCLK,29->AC97_SDI,30->AC97_SDO,31->AC97_SYNC
;32->MMC_CLK,33->nCS5,34->FFRXD,35->FFCTS,36->FFDCD,37->FFDSR,38->FFRI,39->FFTXD
;40->FFDTR,41->FFRTS,42->BTRXD,43->BTTXD,44->BTCTS,45->BTRTS,46->IRRXD,47->IRTXD
;48->nPOE,49->nPWE,50->nPIOR,51->nPIOW,52->PCMCIA RESET,53->BVD2,54->nPCE2,55->nPREG
;56->nPWAIT,57->nIOIS16,58~63->LDD[0~5]
;64~77->LCD,78->nCS2,79->nCS3
;80->nCS4,81->PCMCIA RDY/nIRQ,82->VS1,83->nCD,84->BVD1,85->nPCE1,86->LDD[16],87->LDD[17]
;88->NAND R/nB,89->LED1,90->CIF_D4,91->CIF_D5,92->MMC_DAT0,93~95->KP_DKIN[0~2]
;96->LED4,97->KP_MKIN[3],98->MMC_nCD,99->MMC_WP,100~102->KP_MKIN[0~2],103->KP_MKOUT[0]
;104->KP_MKOUT[1],105->KP_MKOUT[2],106->ext.,107->LED2,108->LED3,109~111->MMC_DAT[1~3]
;112->MMC_CMD,113->AC97_nRST,114->CIF_D1,115->CIF_D3,116->CIF_D2,117->SCL,118->SDA,
;119,120 supported in PXA271,272,273 only!
xlli_GPSR0_value EQU (0x00008408) ; Set registers
xlli_GPSR1_value EQU (0x004FAB82)
xlli_GPSR2_value EQU (0x0021C000)
xlli_GPSR3_value EQU (0x00020000) ; nARST high
xlli_GPCR0_value EQU (0x00010810) ; Clear registers
xlli_GPCR1_value EQU (0x00000000) ; FFUART related
xlli_GPCR2_value EQU (0x00000000)
xlli_GPCR3_value EQU (0x00000000)
xlli_GPDR0_value EQU (0xC0A18DFC) ; Direction Registers
xlli_GPDR1_value EQU (0xFCDFAB83)
xlli_GPDR2_value EQU (0x02E1FFFF)
xlli_GPDR3_value EQU (0x00021B81)
xlli_GAFR0_L_value EQU (0x82000000) ; Alternate function registers
xlli_GAFR0_U_value EQU (0xA5E54018)
xlli_GAFR1_L_value EQU (0x999A955A)
xlli_GAFR1_U_value EQU (0xAAA5A0AA)
xlli_GAFR2_L_value EQU (0xAAAAAAAA)
xlli_GAFR2_U_value EQU (0x55F0A402)
xlli_GAFR3_L_value EQU (0x540A950C)
;xlli_GAFR3_U_value EQU (0x00001599)
xlli_GAFR3_U_value EQU (0x00001591) ; nARST as io to output high for check AC97 chip OSC
;
; MEMORY CONTROLLER SETTINGS FOR MAINSTONE
;
xlli_MDREFR_value EQU (0x0000001E)
IF :DEF: xlli_FLASH_WIDTH_16_BIT
xlli_MSC0_DC_value EQU (0x7FF07FFA) ; PXA27x Card Flash value (MCP version)
ELSE
xlli_MSC0_DC_value EQU (0x7FF0B8F2) ; PXA27x Card Flash value (Non-MCP version)
ENDIF
xlli_MSC0_MS_value EQU (0x23F2B8F2) ; Mainstone Board Flash value
xlli_MSC1_value EQU (0x0000CCD1)
xlli_MSC2_value EQU (0x0000B884)
xlli_MECR_value EQU (0x00000001)
xlli_MCMEM0_value EQU (0x00014307)
xlli_MCMEM1_value EQU (0x00014307)
xlli_MCATT0_value EQU (0x0001C787)
xlli_MCATT1_value EQU (0x0001C787)
xlli_MCIO0_value EQU (0x0001430F)
xlli_MCIO1_value EQU (0x0001430F)
xlli_FLYCNFG_value EQU (0x00010001)
xlli_MDMRSLP_value EQU (0x0000C008)
xlli_SXCNFG_value EQU (0x40044004) ; Default value at boot up
;
; Optimal values for MSCO for various MemClk frequencies are listed below
; These values are for L18 async flash
;
IF :DEF: xlli_C0_BULVERDE
xlli_MSC0_13 EQU (0x11101110)
xlli_MSC0_19 EQU (0x11101110)
xlli_MSC0_26 EQU (0x11201120) ; 26 MHz setting
xlli_MSC0_32 EQU (0x11201120)
xlli_MSC0_39 EQU (0x11301130) ; 39 MHz setting
xlli_MSC0_45 EQU (0x11301130)
xlli_MSC0_52 EQU (0x11401140) ; 52 MHz setting
xlli_MSC0_58 EQU (0x11401140)
xlli_MSC0_65 EQU (0x11501150) ; 65 MHz setting
xlli_MSC0_68 EQU (0x11501150)
xlli_MSC0_71 EQU (0x11501150) ; 71.5 MHz setting
xlli_MSC0_74 EQU (0x11601160)
xlli_MSC0_78 EQU (0x12601260) ; 78 MHz setting
xlli_MSC0_81 EQU (0x12601260)
xlli_MSC0_84 EQU (0x12601260) ; 84.5 MHz setting
xlli_MSC0_87 EQU (0x12701270)
xlli_MSC0_91 EQU (0x12701270) ; 91 MHz setting
xlli_MSC0_94 EQU (0x12701270) ; 94.2 MHz setting
xlli_MSC0_97 EQU (0x12701270) ; 97.5 MHz setting
xlli_MSC0_100 EQU (0x12801280) ; 100.7 MHz setting
xlli_MSC0_104 EQU (0x12801280) ; 104 MHz setting
xlli_MSC0_110 EQU (0x12901290)
xlli_MSC0_117 EQU (0x13901390) ; 117 MHz setting
xlli_MSC0_124 EQU (0x13A013A0)
xlli_MSC0_130 EQU (0x13A013A0) ; 130 MHz setting
xlli_MSC0_136 EQU (0x13B013B0)
xlli_MSC0_143 EQU (0x13B013B0)
xlli_MSC0_149 EQU (0x13C013C0)
xlli_MSC0_156 EQU (0x14C014C0)
xlli_MSC0_162 EQU (0x14C014C0)
xlli_MSC0_169 EQU (0x14C014C0)
xlli_MSC0_175 EQU (0x14C014C0)
xlli_MSC0_182 EQU (0x14C014C0)
xlli_MSC0_188 EQU (0x14C014C0)
xlli_MSC0_195 EQU (0x15C015C0)
xlli_MSC0_201 EQU (0x15D015D0)
;xlli_MSC0_208 EQU (0x15D015D0)
xlli_MSC0_208 EQU (0x15D02AE0) ;hzh
ELSE
; This is a hack to get around some stupid B0 timing issue where it doesn't like the optimal
; values according to it's own SPEC!?! These timing values are relaxed from the above optimal
; but they work for B-step PXA27x... ugh....
xlli_MSC0_13 EQU (0x12101210)
xlli_MSC0_19 EQU (0x12101210)
xlli_MSC0_26 EQU (0x12201220) ; 26 MHz setting
xlli_MSC0_32 EQU (0x12201220)
xlli_MSC0_39 EQU (0x13301330) ; 39 MHz setting
xlli_MSC0_45 EQU (0x13301330)
xlli_MSC0_52 EQU (0x13401340) ; 52 MHz setting
xlli_MSC0_58 EQU (0x13601360)
xlli_MSC0_65 EQU (0x13501350) ; 65 MHz setting
xlli_MSC0_68 EQU (0x13501350)
xlli_MSC0_71 EQU (0x14601460) ; 71.5 MHz setting
xlli_MSC0_74 EQU (0x14601460)
xlli_MSC0_78 EQU (0x14601460) ; 78 MHz setting
xlli_MSC0_81 EQU (0x14701470)
xlli_MSC0_84 EQU (0x14701470) ; 84.5 MHz setting
xlli_MSC0_87 EQU (0x14701470)
xlli_MSC0_91 EQU (0x14701470) ; 91 MHz setting
xlli_MSC0_94 EQU (0x14801480) ; 94.2 MHz setting
xlli_MSC0_97 EQU (0x14801480) ; 97.5 MHz setting
xlli_MSC0_100 EQU (0x15801580) ; 100.7 MHz setting
;xlli_MSC0_104 EQU (0x15801580) ; 104 MHz setting
xlli_MSC0_104 EQU (0x15802AD0) ; 104 MHz setting, hzh
xlli_MSC0_110 EQU (0x15901590)
xlli_MSC0_117 EQU (0x15A015A0) ; 117 MHz setting
xlli_MSC0_124 EQU (0x15A015A0)
xlli_MSC0_130 EQU (0x15B015B0) ; 130 MHz setting
xlli_MSC0_136 EQU (0x16B016B0)
xlli_MSC0_143 EQU (0x16C016C0)
xlli_MSC0_149 EQU (0x16C016C0)
xlli_MSC0_156 EQU (0x16C016C0)
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