constrain.tcl

实现 ASIC前端设计的典型约束脚本输入

#############################################
#name: constrain.tcl
#description: stm_16 tcl script for DC,SMIC18 library
#date:2006-03-26
#author: miter
#version:v1.0
#revised: 2006-03-26
#############################################
read_verilog stm_16.v
#set & link top design ,remove relative constraints
current_design stm_16
link 
reset_design
################
#set clocks
create_clock -period 6 -waveform [list 0 3] -name clk [get_ports clk]
set_clock_latency -source 1 [get_clocks clk]
set_clock_latency 1 [get_clocks clk]
set_clock_uncertainty 0.5 [get_clocks clk]
set_clock_transition 0.3 [get_clocks clk]
set_dont_touch_network [get_clocks clk]
################
#set input delays & output delays
set i_min_delay 1.0
set i_max_delay 3.0
set o_delay 3.0
set tran_delay 0.3
set ain_ports [remove_from_collection [all_inputs] [get_ports clk]]
set_input_delay -min $i_min_delay  -clock [get_clocks clk] $ain_ports
set_input_delay -max $i_max_delay -clock [get_clocks clk] $ain_ports
set_output_delay -max $o_delay -clock [get_clocks clk] [all_outputs]
#set_input_transition $tran_delay $ain_ports
################
#set combinational path delay & timing exception


################
#clk,reset,etc.driven capablity should be strongest
set_drive 0 [list clk reset rearrange]
set_dont_touch_network [list clk reset rearrange]

set_driving_cell -lib_cell AND2HD1X -pin Z -library smic18_tt -no_design_rule \
              [remove_from_collection $ain_ports [get_ports [list reset rearrange]]] 
set_load 0.3 [all_outputs]
################
#ensure the postive slack,the smallest area
set_max_area 0
#report_lib smic18_tt
set_operating_condition -max_library  smic18_ss -max worst \
                   -min_library  smic18_tt -min typical            
#wire_load_models ??
#set auto_wire_load_selection true
set_wire_load_model -name reference_area_20000 -library smic18_tt
set_wire_load_mode enclosed
#################
#set DRC check

#################
#recommend for reduce area
set compile_sequential_area_recovery true
set compile_new_boolean_structure true
set_structure -boolean true -boolean_effort high
#fix the multiple port nets
set_fix_multiple_port_nets -all -buffer
#################
check_design > check_design.rpt
check_timing > check_timing.rpt
#################
uniquify
compile 
compile -map_effort high -incremental_mapping 
#reports
report_timing -delay max -max_paths 1 > timing_setup.rpt
report_timing -delay min -max_paths 1 > timing_hold.rpt
report_constraint -all_violators > con_violators.rpt
#write the database
change_names -rule verilog -h
write -format verilog -hier -output stm_16.sv
write_sdf stm_16.sdf
write_constraints -format sdf -cover_design -output constraints.sdf
write_sdc stm_16.sdc