📄 boot.s
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;*$Id: boot.s, 2009/01/12 23:30:12 huguangfu Exp $ */
;************************************************************************
; *
; * Title :boot.s
; *
; * Summary :boot
; *
; * Author :hgf
; *
; * Date :2009-01-12
; *
; * Copyright (c) Pioneer Corporation
; *
;*************************************************************************/
;define the size of stack
USR_STACK_LEGTH EQU 0x20c
SVC_STACK_LEGTH EQU 0x20
FIQ_STACK_LEGTH EQU 0
IRQ_STACK_LEGTH EQU 0x1000
ABT_STACK_LEGTH EQU 0
UND_STACK_LEGTH EQU 0
NoInt EQU 0x80
USR32Mode EQU 0x10
SVC32Mode EQU 0x13
SYS32Mode EQU 0x1f
IRQ32Mode EQU 0x12
FIQ32Mode EQU 0x11
GET sfr.inc
IMPORT __main ;The entry of C library
IMPORT irq_vector
IMPORT fiq_vector
IMPORT InitUart
IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit||
IMPORT ||Image$$ARM_LIB_STACK$$Base||
IMPORT InitMMU
EXPORT Reset
PRESERVE8
CODE32
AREA vectors,CODE,READONLY
ENTRY
;Interrupt vectors
Reset
LDR PC, ResetAddr
LDR PC, UndefinedAddr
LDR PC, SWI_Addr
LDR PC, PrefetchAddr
LDR PC, DataAbortAddr
DCD 0xe1a00000 ;nop
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
ResetAddr DCD ResetInit
UndefinedAddr DCD Undefined
SWI_Addr DCD SoftwareInterrupt
PrefetchAddr DCD PrefetchAbort
DataAbortAddr DCD DataAbort
Nouse DCD 0
;IRQ_Addr DCD irq_vector
IRQ_Addr DCD irq_asm_vector
FIQ_Addr DCD fiq_vector
;Undefined Instruction
Undefined
B Undefined
;SWI
SoftwareInterrupt
B SoftwareInterrupt
;PrefetchAbort
PrefetchAbort
B PrefetchAbort
;Data Abort
DataAbort
B DataAbort
irq_asm_vector
SUB lr, lr, #4
STMFD sp!, {r0-r12, lr} ;push r0-r12 register file and lr( pc return address )
MRS r4, spsr
STMFD sp!, {r4} ;push current spsr_irq ( =cpsr_svc )
ldr r0, =0x10140000
ldr r4, [r0, #48]
mov r0, #&0
ldr r1, =0x10140000
str r0, [r1, #48]
cmp r4, #&0
beq _nottimerisr
blx r4
_nottimerisr
LDMFD sp!, {r4} ;get cpsr_svc from stack
MSR SPSR_cxsf, r4 ;prepare spsr to return svc mode
LDMFD sp!, {r0-r12, pc}^
;*****************************************************************
;*
;* Function Name
;* ResetInit
;* Inputs
;* None
;* Outputs
;* None
;* Return Codes
;* None
;* Description
;* This funtion reset route
;* Date:
;* 2008-03-04
;*****************************************************************/
ResetInit
BL SystemCtrl ;the system config
WarmReset
BL InitStack ;init the stack of system
BL InitUart
BL CopyIntVector ;copy Interrupt vector to sdram
BL InitMMU
B __main
;*****************************************************************
;*
;* Function Name
;* SystemCtrl
;* Inputs
;* None
;* Outputs
;* None
;* Return Codes
;* None
;* Description
;* This funtion init the system
;* Date:
;* 2008-03-04
;*****************************************************************/
SystemCtrl
;mov sp, #&01000000
;stmfd r13!, {lr}
;disable all interrupt
mrs r1, cpsr
orr r1, r1, #0xc0
msr cpsr_c, r1
;dll config
ldr r1, =&101c0e0c ;=101c0e0c(Decoder(HOSTIF))
mov r0, #&0
str r0, [r1,#0]
ldr r0, =&0100300c ;fullseg loader
;ldr r0, =&0B00300c ;me
ldr r1, =APB_SCPLLFCTRL ;=101e0018(SystemController(SCPLLFCTRL))
str r0, [r1,#0]
ldr r0, =&0ffc0003
ldr r1, =APB_SCPLLCTRL ;101e0014(SystemController(SCPLLCTRL))
str r0, [r1,#0]
ldr r1, =APB_SCCTRL ;=101e0000(SystemController(SCCTRL))
ldr r0, [r1,#0]
;and r0, r0,#&f8 ;fullseg loader
and r0, r0,#&1f8 ;me for remapclr
orr r0, r0,#&4
bic r0, r0,#&7000
orr r0, r0,#&1000
orr r0, r0,#&550000
str r0, [r1,#0]
wait_lock
ldr r0, =APB_SCCTRL ;101e0000(SystemController(SCCTRL))
ldr r0, [r0,#0]
and r0, r0,#&78
cmp r0, #&20
bne wait_lock ;wait pll lock
;smc config
mov r0, #&55
ldr r1, =SMC_DBWCR ;10100000(SMC(DBWCR))
str r0, [r1,#0]
ldr r0, =&00009999
ldr r1, =SMC_WSCR ;10100008(SMC(EDWCR))
str r0, [r1,#0]
ldr r0, =&00001111
ldr r1, =SMC_TAREA ;10100010(SMC(TAREA))
str r0, [r1,#0]
ldr r0, =&00001111
ldr r1, =SMC_TACSR ;10100014(SMC(TACSR))
str r0, [r1,#0]
ldr r0, =&00001111
ldr r1, =SMC_TCOSR ;10100018(SMC(TCOSR))
str r0, [r1,#0]
ldr r0, =&00001111
ldr r1, =SMC_TCOHR ;1010001c(SMC(TCOHR))
str r0, [r1,#0]
ldr r1, =APB_SCCTRL ;101e0000(SystemController(SCCTRL))
ldr r0, [r1,#0]
orr r0, r0,#&100 ;clr memory remap
str r0, [r1,#0]
ldr r0, =&000186a0
delay
sub r0, r0,#&1
cmp r0, #&0
bne delay ;loop wait 100000 times
;mov r0, #&2
;ldr r1, &3000031c ;101e3028 timer4setup
;str r0, [r1,#0]
;mov r0, #&2
;ldr r1, &3000031c
;str r0, [r1,#0]
;mov r0, #&2
;ldr r1, &3000031c
;str r0, [r1,#0]
;mov r0, #&82
;ldr r1, &3000031c
;str r0, [r1,#0]
ldr r0, =&f73bf084
ldr r1, =APB_SCPERCTRL0 ;101e001c(SystemController(SCPERCTRL0))
str r0, [r1,#0]
ldr r0, =&f7e2f7cf
ldr r1, =APB_SCPEREN ;101e0024(SystemController(SCPEREN))
str r0, [r1,#0]
;ldmfd r13!, {pc}
mov pc, lr
;*****************************************************************
;*
;* Function Name
;* InitStack
;* Inputs
;* None
;* Outputs
;* None
;* Return Codes
;* None
;* Description
;* This funtion init the system stack
;* Date:
;* 2008-03-04
;*****************************************************************/
InitStack
MOV R0, LR
;set the stack of supervisor mode
MSR CPSR_c, #0xd3
LDR SP, StackSvc
;;set the stack of irq mode
MSR CPSR_c, #0xd2
LDR SP, StackIrq
;;set the stack of fiq mode
MSR CPSR_c, #0xd1
LDR SP, StackFiq
;;set the stack of abort mode
MSR CPSR_c, #0xd7
LDR SP, StackAbt
;;set the stack of undefined mode
MSR CPSR_c, #0xdb
LDR SP, StackUnd
;;set the stack of system mode
MSR CPSR_c, #0xdf
;LDR SP, =StackUsr
LDR SP, =||Image$$ARM_LIB_STACK$$ZI$$Limit||
MOV PC, R0
;*****************************************************************
;*
;* Function Name
;* CopyIntVector
;* Inputs
;* None
;* Outputs
;* None
;* Return Codes
;* None
;* Description
;* This funtion copy Interrupt vector
;* Date:
;* 2008-03-04
;*****************************************************************/
CopyIntVector
mov r0, #&0
ldr r1, =Reset
ldr r2, [r1,#4]
str r2, [r0,#4] ;undef_vector
ldr r2, [r1,#36]
str r2, [r0,#36]
ldr r2, [r1,#8]
str r2, [r0,#8] ;swi_vector
ldr r2, [r1,#40]
str r2, [r0,#40]
ldr r2, [r1,#24] ;irq_vector
str r2, [r0,#24]
ldr r2, [r1,#56]
str r2, [r0,#56]
ldr r2, [r1,#28] ;firq_vector
str r2, [r0,#28]
ldr r2, [r1,#60]
str r2, [r0,#60]
ldr r2, [r1,#12] ;pref_abort_vector
str r2, [r0,#12]
ldr r2, [r1,#44]
str r2, [r0,#44]
ldr r2, [r1,#16] ;data_abort_vector
str r2, [r0,#16]
ldr r2, [r1,#48]
str r2, [r0,#48]
mov r0, #&0
ldr r1, =Reset
ldr r2, [r1,#0]
str r2, [r0,#0] ;reset_vector
ldr r2, =WarmReset
str r2, [r0,#32] ;reset_address
mov pc, lr
StackSvc DCD SvcStackSpace + (SVC_STACK_LEGTH - 1)* 4
StackIrq DCD IrqStackSpace + (IRQ_STACK_LEGTH - 1)* 4
StackFiq DCD FiqStackSpace + (FIQ_STACK_LEGTH - 1)* 4
StackAbt DCD AbtStackSpace + (ABT_STACK_LEGTH - 1)* 4
StackUnd DCD UndtStackSpace + (UND_STACK_LEGTH - 1)* 4
AREA MyStacks, DATA, NOINIT, ALIGN=4
SvcStackSpace SPACE SVC_STACK_LEGTH * 4 ;the memory of svc mode
IrqStackSpace SPACE IRQ_STACK_LEGTH * 4 ;the memory of irq mode
FiqStackSpace SPACE FIQ_STACK_LEGTH * 4 ;the memory of fiq mode
AbtStackSpace SPACE ABT_STACK_LEGTH * 4 ;the memory of abort mode
UndtStackSpace SPACE UND_STACK_LEGTH * 4 ;the memory of undefined mode
END
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