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📄 cp15.s

📁 ucos 在 arm9 芯片上的移植
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;*$Id: cp15.s,v 1.3 2008/05/13 03:21:06 xuhongliang Exp $ */
;************************************************************************
; *
; * Title		:cp15.s
; *
; * Summary		:cp15
; *
; * Author		:xhl
; *
; * Date                :2008-03-05
; *
; * Copyright (c) Pioneer Corporation
; *
;*************************************************************************/
SECTABLE_ADDR		EQU	0x03ff8000
PAGETABLE_ADDR		EQU	0x03ff8000

	GET sfr.inc
	;import the extern funtion
        
	;export funtion for extern use
	EXPORT  InitMMU
        
	PRESERVE8
	CODE32

	AREA    CP15, CODE,READONLY
	
InitMMU
	mrc            	p15,0,r1,c0,c0,0   	;c0->ID Code Register                                                                          
	ldr            	r0,=&00069260                                                                                      
	and            	r1,r1,r0                                                                                                          
	cmp            	r1,r0                                                                                                             
	bne            	mmuend          	;id error return                                                                               
	;xhl add       	
	mrc            	p15,0,r1,c1,c0,0
	tst		r1, #&01
	beq		MMUNoUse
tci_loop
	mrc		p15, 0, r15, c7, c14, 3
	bne		tci_loop
	mov		r0,#&0  
	mcr            	p15,0,r0,c7,c5,0	
MMUNoUse
	ldr	     	r0,=&0001005
	bic		r1,r1,r0
	mcr            	p15,0,r1,c1,c0,0
	;xhl add end   	
	mov            	r2,#&0                                                                                                            
	mcr            	p15,0,r2,c8,c7,0   	;Invalidate TLB                                                                                
	ldr            	r1,=SECTABLE_ADDR                                                                                      
	mov            	r2,#&1000          	;Translation Table 4096 entries                                                                
	mov            	r0,#&0                                                                                                            
loop_clr_TTBR          	
	cmp            	r2,r0                                                                                                             
	strne          	r0,[r1],#4                                                                                                        
	subne          	r2,r2,#&1                                                                                                         
	bne            	loop_clr_TTBR          	;loop clear 0x03ef0000 len 16K                                                                 
	ldr            	r5,=memregions                                                                                     
	ldr            	r8,=PAGETABLE_ADDR                                                                                      
loopnextsection        	
	ldr            	r4,[r5],#4         	;section size                                                                      
	cmp            	r4,#&0             	                                                                                               
	beq            	tabelend          	;size of 0 means finish                                                                        
	ldr            	r0,[r5],#4         	;offset of memory                                                                  
	ldr            	r6,[r5],#4         	;descriptor                                                                        
	ldr            	r7,[r5],#4         	;descriptor                                                                         
	ldr            	r1,=SECTABLE_ADDR  	;Section Table address                                                                                
	mov            	r2,r0,lsr #20      	;section is 1M times                                                                           
	add            	r1,r1,r2,lsl #2    	;section table is 4 bytes(make section table addr)                                             
loopinsection          	
	cmp            	r4,#&100000        	;1M                                                                                            
	blt            	pagemode          	;must greater 1M memory                                                                        
	sub            	r4,r4,#&100000     	;eche section table is 1M                                                                      
	ldr            	r0,=&fff00000      	                                                                                
	and            	r0,r6,r0           	;make section descriptor                                                                       
	orr            	r0,r0,r7           	                                                                                               
	orr            	r0,r0,#&12         	;section descriptor                                                                            
	str            	r0,[r1],#4         	;store section table                                                                           
	add            	r6,r6,#&100000                                                                                                    
	b              	loopinsection                                                                                                         
pagemode	       													 
	cmp            	r4,#&0                                                                                                            
	beq            	loopnextsection          ;a section end,loop next                                                                       
	ldr            	r0,=&fffffc00      	                                                                                
	ldr            	r2,[r1,#0]         	;section table addr                                                                            
	cmp            	r2,#&0                                                                                                            
	andne          	r3,r2,r0                                                                                                          
	bne            	pagetable		;first leve descriptor exist                                                                                                         
	and            	r8,r8,r0           	;R8->Page Table address                                                                        
	orr            	r0,r8,#&11         	;Coarse page table                                                                             
	str            	r0,[r1,#0]         	;store coarse page table base address                                                          
	mov            	r3,r8              	                                                                                               
	mov            	r2,#&100           	;256 small page                                                                                
	mov            	r0,#&0                                                                                                            
loopclrpagetable       	
	cmp            	r2,r0                                                                                                             
	strne          	r0,[r8],#4                                                                                                        
	subne          	r2,r2,#&1                                                                                                         
	bne            	loopclrpagetable    	;loop clear page table 256*4                                                                   
pagetable	       													 
	mov            	r1,#&c                                                                                                            
	and            	r1,r7,r1           	;section descriptor                                                                            
	mov            	r0,#&c00                                                                                                          
	and            	r0,r7,r0                                                                                                          
	mov            	r0,r0,lsr #10                                                                                                     
	add            	r0,r0,r0,lsl #2                                                                                                   
	add            	r0,r0,r0,lsl #4                                                                                                   
	mov            	r7,#&0                                                                                                            
	add            	r7,r1,r0,lsl #4    	;make small page AP                                                                            
	ldr            	r1,[r5,#-12]       	;descriptor                                                                                    
	mov            	r0,#&ff000                                                                                                        
	and            	r1,r1,r0           	;make small page descriptor                                                                    
	mov            	r1,r1,lsr #12                                                                                                     
	add            	r3,r3,r1,lsl #2                                                                                                   
loopinpage             	
	cmp            	r4,#&1000                                                                                                         
	blt            	loopnextsection         ;<4K memory, system not use                                                                    
	sub            	r4,r4,#&1000       	;page size is 4K                                                                               
	ldr            	r0,=&fffff000                                                                                      
	and            	r0,r6,r0                                                                                                          
	orr            	r0,r0,r7                                                                                                          
	orr            	r0,r0,#&2                                                                                                         
	str            	r0,[r3],#4                                                                                                        
	add            	r6,r6,#&1000                                                                                                      
	b              	loopinpage                                                                                                         
tabelend	       													 
	ldr            	r0,=SECTABLE_ADDR                                                                                      
	mcr            	p15,0,r0,c2,c0,0   	;write TTBR                                                                                    
	ldr            	r2,=&55555555      	                                                                                
	mcr            	p15,0,r2,c3,c0,0   	;write Domain access permissions                                                               
	mov            	r0,#&0             	                                                                                               
	mcr            	p15,0,r0,c13,c0,0  	;write FCSE PID Register                                                                       

	;mrc            	p15,0,r0,c1,c0,0   	;Read Control Register                                                                         
	;ldr            	r1,=&fffa0c00      	                                                                                
	;bic            	r0,r0,r1           	;clear SBZ bits                                                                                
	;ldr            	r1,=&00050078      	                                                                                
	;orr            	r0,r0,r1           	;set SBO bits                                                                                  
	;bic            	r0,r0,#&80         	;Little-endian                                                                                 
	;orr            	r0,r0,#&1          	;MMU enable                                                                                    
	;orr            	r0,r0,#&1000       	;ICache enable                                                                                 
	;orr            	r0,r0,#&4          	;DCache enable                                                                                 
	;mcr            	p15,0,r0,c1,c0,0   	;write Control Register                                                                        
	;mov            	r3,pc                                                                                                             
	;ldr            	r2,[r3,#0]                                                                                                        
	;ldr            	r2,[r3,#0]                                                                                                        
	;ldr            	r2,[r3,#0]                                                                                                        

	; add xhl
	; flush TLBs
	mov 		r0, #0
	nop
	nop
	mcr      	p15, #0, r0, c8, c5, #0
	nop
	nop
	nop
	nop		             	
	mcr      	p15, #0, r0, c8, c6, #0
	nop
	nop
	nop
	nop		             	
	
	; flush cache	             	
	mov 		r0, #0
	nop
	nop
	mcr      	p15, #0, r0, c7, c5, #0
	nop
	nop
	nop
	nop		              
	mcr      	p15, #0, r0, c7, c6, #0
	nop
	nop
	nop
	nop		             	
		
	; enable the instruction cache and data cache
	mrc   		p15, #0, r1, c1, c0, #0
	mov   		r0,#0x1000
	orr   		r1, r1, r0                    	; enable IC
	nop   		                              	; avoid LATECANCEL bug
	mcr   		p15, #0, r1, c1, c0, #0
	nop                                 		; avoid LATECANCEL bug and allow pipe
	nop                                 		; to empty
	nop
	nop 
	
	mrc   		p15, #0, r1, c1, c0, #0
	mov   		r0,#5
	orr   		r1, r1, r0                    	; enable DC, MMU (DC - 4, MMU - 1)
	nop   		                              	; avoid LATECANCEL bug
	mcr   		p15, #0, r1, c1, c0, #0
	nop   		
	nop   		
	nop   		
	nop   		
	mrc   		p15, #0, r1, c1, c0, #0	   	; verify 
	nop                              
	nop
	nop
	nop 
        
	; flush TLBs
	mov 		r0, #0
	nop
	nop
	mcr      	p15, #0, r0, c8, c5, #0
	nop      	
	nop      	
	nop      	
	nop	 	       		
	mcr      	p15, #0, r0, c8, c6, #0
	nop
	nop
	nop
	nop				
	
        
	; flush cache			
	mov 		r1, #0
	nop
	nop
	mcr      	p15, #0, r0, c7, c5, #0
	nop      	
	nop      	
	nop      	
	nop	 	        		
	mcr      	p15, #0, r0, c7, c6, #0
	nop
	nop
	nop
	nop	         		
        
	mov     	pc, r14		; Go back to where cache() is called from 
	
		          	
	nop
	nop
	nop
	nop
	;xhl add end
mmuend                 	
	bx             	lr                                                                                                                


memregions
	DCD	0x04000000	;size
	DCD	0x00000000	;offset
	DCD	0x00000000	;Description
	DCD	0x00000c0c	;Description
	DCD	0x04000000
	DCD	0x04000000
	DCD	0x04000000
	DCD	0x00000c00
	DCD	0x02000000
	DCD	0x08000000
	DCD	0x08000000
	DCD	0x00000c00
	DCD	0x00100000
	DCD	0x10100000
	DCD	0x10100000
	DCD	0x00000c00
	DCD	0x02000000
	DCD	0x30000000
	DCD	0x30000000
	DCD	0x00000c00
	DCD	0x01000000
	DCD	0x38000000
	DCD	0x38000000
	DCD	0x00000c00
	DCD	0x00800000
	DCD	0x40000000
	DCD	0x40000000
	DCD	0x00000c00
	DCD	0x00100000
	DCD	0x48000000
	DCD	0x48000000
	DCD	0x00000c00
	DCD	0x00000000

;*****************************************************************
;*
;* Function Name
;*    ARM_disableIRQ
;* Inputs
;*    None
;* Outputs
;*    None
;* Return Codes
;*    None
;* Description
;*   Disable IRQ interrupt for ARM  
;* Date:
;*    2008-03-06
;*****************************************************************/
	EXPORT  ARM_disableIRQ
ARM_disableIRQ
	stmfd 	r13!, {r0-r2}
	mrs 	r1, cpsr
	and 	r2, r1, #0x1F
	cmp 	r2, #0x12        	;see if currently in IRQ mode
	bne 	disableIRQ       	;If not in IRQ mode, continue
	ldmfd 	r13!, {r0-r2}
	bx 	lr
    
disableIRQ
	orr 	r1, r1, #0x80		;disable IRQ
	msr 	cpsr_c, r1
	ldmfd 	r13!, {r0-r2}
	;movs 	pc, lr
	mov 	pc, lr
;*****************************************************************
;*
;* Function Name
;*    ARM_enableIRQ
;* Inputs
;*    None
;* Outputs
;*    None
;* Return Codes
;*    None
;* Description
;*   Enable IRQ interrupt for ARM  
;* Date:
;*    2008-03-06
;*****************************************************************/
	EXPORT  ARM_enableIRQ
ARM_enableIRQ
	stmfd 	r13!, {r0-r2}

	mrs 	r1, cpsr
	and 	r2, r1, #0x1F
	cmp 	r2, #0x12       	; see if currently in IRQ mode
	bne 	enableIRQ        	; If not in IRQ mode, continue
	ldmfd 	r13!, {r0-r2}
	bx 	r14          		

enableIRQ
	bic 	r1, r1, #0x80    	; enable IRQ 
	msr 	cpsr_c, r1
	ldmfd 	r13!, {r0-r2}

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