📄 inth.c
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/*$Id: inth.c,v 1.5 2008/05/27 23:30:22 xuhongliang Exp $ */
/************************************************************************
*
* Title :inth
*
* Summary :the handle of interrupt
*
* Author :xhl
*
* Date :2008-03-05
*
* Copyright (c) Pioneer Corporation
*
*************************************************************************/
#include "sfr.h"
#include "DRV_VIC.h"
extern volatile LC_VIC* lcVIC;
/**
\brief IRQ interrupt despatcher
This routine is the IRQ interrupt service routine. It finds the interrupt \n
pending and calls the ISR from the ISR table entry
\return None
*/
__irq void irq_vector(void)
{
#if 1
INTC_ISR pirq;
//get pointer to interrupt entry table
pirq = (INTC_ISR)lcVIC->VICVectAddr;
lcVIC->VICVectAddr = 0;
if(pirq != 0)
pirq();
#endif
}
/**
\brief FIQ interrupt despatcher
This routine is the FIQ interrupt service routine. It finds the interrupt \n
pending and calls the ISR from the ISR table entry
\return None
*/
__irq void fiq_vector(void)
{
//INTC_ISR pirq;
//get pointer to interrupt entry table
//pirq = (INTC_ISR)INTC_getFIQPendIntAddress();
//pirq();
}
#if 0
/**
\brief SWI interrupt despatcher
This routine is the SWI interrupt service routine. Calls the routine to service SWI interrupts
\return None
*/
int SemiHosting(int *Regs);
void SWI_Exception(int SWI_Num, int *Regs)
{
int Fun_Num;
switch(SWI_Num)
{
case 0x123456:
// Regs[0] = SemiHosting(Regs);
break;
case 0x10:
Fun_Num = Regs[0];
break;
default:
break;
}
}
//__swi(0x00) void swi_00(void);
//{
//go_swi();
//}
#ifndef RTOS_NONE
extern void vputstr(char*);
extern void vputc(char);
void PrintHex(unsigned int val)
{
int i;
char c;
for(i=7; i>=0; i--) {
c = (val>>(i*4)) & 0x0000000f;
if(c<0xa) {
c += '0';
vputc(c);
} else if(c>=0x0a) {
c = c -0x0a + 'A';
vputc(c);
}
}
}
void PrintErrorStatus(unsigned int *SP)
{
//SP:CPSR,R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR
unsigned int id;
get_tid(&id);
vputstr("The run task ID: 0x");
PrintHex(id);
vputstr("\r\n");
vputstr("The ARM Registers:\r\n");
vputstr(" A1:");
PrintHex(SP[1]);
vputstr(" A2:");
PrintHex(SP[2]);
vputstr(" A3:");
PrintHex(SP[3]);
vputstr(" A4:");
PrintHex(SP[4]);
vputstr("\r\n");
vputstr(" V1:");
PrintHex(SP[5]);
vputstr(" V2:");
PrintHex(SP[6]);
vputstr(" V3:");
PrintHex(SP[7]);
vputstr(" V4:");
PrintHex(SP[8]);
vputstr(" V5:");
PrintHex(SP[9]);
vputstr(" V6:");
PrintHex(SP[10]);
vputstr("\r\n");
vputstr(" SL:");
PrintHex(SP[11]);
vputstr(" FP:");
PrintHex(SP[12]);
vputstr(" IP:");
PrintHex(SP[13]);
vputstr(" LR:");
PrintHex(SP[14]);
vputstr(" CPSR:");
PrintHex(SP[0]);
}
/**
\brief Data abort interrupt handler
This routine is the Data abort interrupt handler,
\warning Does nothing
\return None
*/
void data_abort_vector(unsigned int *SP)
{
vputstr("\r\n\r\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r\n");
vputstr("Data abort exception:\r\n");
PrintErrorStatus(SP);
vputstr("\r\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r\n");
while(1);
}
/**
\brief Undefined instruction interrupt handler
This routine is the Undefined instruction interrupt handler,
\warning Does nothing
\return None
*/
void undef_vector(unsigned int *SP)
{
vputstr("\r\n\r\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r\n");
vputstr("Undefined instruction exception:\r\n");
PrintErrorStatus(SP);
vputstr("\r\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r\n");
while(1);
}
/**
\brief Prefetch abort interrupt handler
This routine is the Prefetch abort interrupt handler,
\warning Does nothing
\return None
*/
void pref_abort_vector(unsigned int *SP)
{
vputstr("\r\n\r\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r\n");
vputstr("Prefetch abort exception:\r\n");
PrintErrorStatus(SP);
vputstr("\r\n!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\r\n");
while(1);
}
/**
\brief Reset System interrupt handler
This routine is the Reset system interrupt handler,
\warning Does nothing
\return None
*/
#endif
__irq void reset_system(void)
{
while(1);
}
#endif
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