📄 cp15.lst
字号:
e, continue
339 00000378 E8BD0007 ldmfd r13!, {r0-r2}
340 0000037C E12FFF1E bx r14
341 00000380
342 00000380 enableIRQ
343 00000380 E3C11080 bic r1, r1, #0x80 ; enable IRQ
344 00000384 E121F001 msr cpsr_c, r1
345 00000388 E8BD0007 ldmfd r13!, {r0-r2}
ARM Macro Assembler Page 14
346 0000038C ;movs pc, r14
347 0000038C E1A0F00E mov pc, r14
348 00000390 ;*******************************************************
**********
349 00000390 ;*
350 00000390 ;* Function Name
351 00000390 ;* ARM_disableFIQ
352 00000390 ;* Inputs
353 00000390 ;* None
354 00000390 ;* Outputs
355 00000390 ;* None
356 00000390 ;* Return Codes
357 00000390 ;* None
358 00000390 ;* Description
359 00000390 ;* Disable FIQ interrupt for ARM
360 00000390 ;* Date:
361 00000390 ;* 2008-03-06
362 00000390 ;*******************************************************
**********/
363 00000390 EXPORT ARM_disableFIQ
364 00000390 ARM_disableFIQ
365 00000390 E92D0007 stmfd r13!, {r0-r2}
366 00000394
367 00000394 E10F1000 mrs r1, cpsr
368 00000398 E201201F and r2, r1, #0x1F
369 0000039C E3520011 cmp r2, #0x11 ; see if currently
in FIQ mode
370 000003A0 1A000001 bne disableFIQ ; If not in FIQ mod
e, continue
371 000003A4 E8BD0007 ldmfd r13!, {r0-r2}
372 000003A8 E12FFF1E bx r14
373 000003AC
374 000003AC disableFIQ
375 000003AC E3811040 orr r1, r1, #0x40 ; disable FIQ
376 000003B0 E121F001 msr cpsr_c, r1
377 000003B4 E8BD0007 ldmfd r13!, {r0-r2}
378 000003B8 ;movs pc, r14
379 000003B8 E1A0F00E mov pc, r14
380 000003BC ;*******************************************************
**********
381 000003BC ;*
382 000003BC ;* Function Name
383 000003BC ;* ARM_enableFIQ
384 000003BC ;* Inputs
385 000003BC ;* None
386 000003BC ;* Outputs
387 000003BC ;* None
388 000003BC ;* Return Codes
389 000003BC ;* None
390 000003BC ;* Description
391 000003BC ;* Disable FIQ interrupt for ARM
392 000003BC ;* Date:
393 000003BC ;* 2008-03-06
394 000003BC ;*******************************************************
**********/
395 000003BC EXPORT ARM_enableFIQ
396 000003BC ARM_enableFIQ
397 000003BC E92D0007 stmfd r13!, {r0-r2}
398 000003C0
ARM Macro Assembler Page 15
399 000003C0 E10F1000 mrs r1, cpsr
400 000003C4 E201201F and r2, r1, #0x1F
401 000003C8 E3520011 cmp r2, #0x11
402 000003CC 1A000001 bne enableFIQ
403 000003D0 E8BD0007 ldmfd r13!, {r0-r2}
404 000003D4 E12FFF1E bx r14
405 000003D8
406 000003D8 enableFIQ
407 000003D8 E3C11040 bic r1, r1, #0x40 ; enable FIQ
408 000003DC E121F001 msr cpsr_c, r1
409 000003E0 E8BD0007 ldmfd r13!, {r0-r2}
410 000003E4 ;movs pc, r14
411 000003E4 E1A0F00E mov pc, r14
412 000003E8 ;*******************************************************
**********
413 000003E8 ;*
414 000003E8 ;* Function Name
415 000003E8 ;* ARM_enableICache
416 000003E8 ;* Inputs
417 000003E8 ;* None
418 000003E8 ;* Outputs
419 000003E8 ;* None
420 000003E8 ;* Return Codes
421 000003E8 ;* None
422 000003E8 ;* Description
423 000003E8 ;* Enable I-Cache on CP15 for ARM
424 000003E8 ;* Date:
425 000003E8 ;* 2008-03-06
426 000003E8 ;*******************************************************
**********/
427 000003E8 EXPORT ARM_enableICache
428 000003E8 ARM_enableICache
429 000003E8 E92D0003 stmfd r13!, {r0-r1}
430 000003EC EE111F10 mrc p15, #0, r1, c1, c0, #0
431 000003F0 E3A00A01 mov r0,#0x1000
432 000003F4 E1811000 orr r1, r1, r0
433 000003F8 E1A00000 nop
434 000003FC E1A00000 nop
435 00000400 EE011F10 mcr p15, #0, r1, c1, c0, #0
436 00000404 E1A00000 nop
437 00000408 E1A00000 nop
438 0000040C E8BD0003 ldmfd r13!, {r0-r1}
439 00000410 E1B0F00E movs pc, r14
440 00000414
441 00000414 ;*******************************************************
**********
442 00000414 ;*
443 00000414 ;* Function Name
444 00000414 ;* ARM_disableICache
445 00000414 ;* Inputs
446 00000414 ;* None
447 00000414 ;* Outputs
448 00000414 ;* None
449 00000414 ;* Return Codes
450 00000414 ;* None
451 00000414 ;* Description
452 00000414 ;* Disable I-Cache on CP15 for ARM
453 00000414 ;* Date:
454 00000414 ;* 2008-03-06
ARM Macro Assembler Page 16
455 00000414 ;*******************************************************
**********/
456 00000414 EXPORT ARM_disableICache
457 00000414 ARM_disableICache
458 00000414 E92D0003 stmfd r13!, {r0-r1}
459 00000418 EE111F10 mrc p15, #0, r1, c1, c0, #0
460 0000041C E3A00A01 mov r0,#0x1000
461 00000420 E1C11000 bic r1, r1, r0
462 00000424 E1A00000 nop
463 00000428 E1A00000 nop
464 0000042C EE011F10 mcr p15, #0, r1, c1, c0, #0
465 00000430 E1A00000 nop
466 00000434 E1A00000 nop
467 00000438 E8BD0003 ldmfd r13!, {r0-r1}
468 0000043C E1B0F00E movs pc, r14
469 00000440 ;*******************************************************
**********
470 00000440 ;*
471 00000440 ;* Function Name
472 00000440 ;* ARM_enableDCache
473 00000440 ;* Inputs
474 00000440 ;* None
475 00000440 ;* Outputs
476 00000440 ;* None
477 00000440 ;* Return Codes
478 00000440 ;* None
479 00000440 ;* Description
480 00000440 ;* Enable D-Cache on CP15 for ARM
481 00000440 ;* Date:
482 00000440 ;* 2008-03-06
483 00000440 ;*******************************************************
**********/
484 00000440 EXPORT ARM_enableDCache
485 00000440
486 00000440 ;warning MMU must be enabled and translation table setup
before
487 00000440 ;data cache can be enabled
488 00000440 ARM_enableDCache
489 00000440 E92D0003 stmfd r13!, {r0-r1}
490 00000444 EE111F10 mrc p15, #0, r1, c1, c0, #0
491 00000448 E3A00004 mov r0,#0x0004
492 0000044C E1811000 orr r1, r1, r0
493 00000450 E1A00000 nop
494 00000454 E1A00000 nop
495 00000458 EE011F10 mcr p15, #0, r1, c1, c0, #0
496 0000045C E1A00000 nop
497 00000460 E1A00000 nop
498 00000464 E8BD0003 ldmfd r13!, {r0-r1}
499 00000468 E1B0F00E movs pc, r14
500 0000046C
501 0000046C ;*******************************************************
**********
502 0000046C ;*
503 0000046C ;* Function Name
504 0000046C ;* ARM_disableDCache
505 0000046C ;* Inputs
506 0000046C ;* None
507 0000046C ;* Outputs
508 0000046C ;* None
ARM Macro Assembler Page 17
509 0000046C ;* Return Codes
510 0000046C ;* None
511 0000046C ;* Description
512 0000046C ;* Disable D-Cache on CP15 for ARM
513 0000046C ;* Date:
514 0000046C ;* 2008-03-06
515 0000046C ;*******************************************************
**********/
516 0000046C EXPORT ARM_disableDCache
517 0000046C ARM_disableDCache
518 0000046C E92D0003 stmfd r13!, {r0-r1}
519 00000470 EE111F10 mrc p15, #0, r1, c1, c0, #0
520 00000474 E3A00004 mov r0,#0x0004
521 00000478 E1C11000 bic r1, r1, r0
522 0000047C E1A00000 nop
523 00000480 E1A00000 nop
524 00000484 EE011F10 mcr p15, #0, r1, c1, c0, #0
525 00000488 E1A00000 nop
526 0000048C E1A00000 nop
527 00000490 E8BD0003 ldmfd r13!, {r0-r1}
528 00000494 E1B0F00E movs pc, r14
529 00000498
530 00000498 ;*******************************************************
**********
531 00000498 ;*
532 00000498 ;* Function Name
533 00000498 ;* ARM_enableMMU
534 00000498 ;* Inputs
535 00000498 ;* None
536 00000498 ;* Outputs
537 00000498 ;* None
538 00000498 ;* Return Codes
539 00000498 ;* None
540 00000498 ;* Description
541 00000498 ;* Enable MMU on CP15 for ARM
542 00000498 ;* Date:
543 00000498 ;* 2008-03-06
544 00000498 ;*******************************************************
**********/
545 00000498 EXPORT ARM_enableMMU
546 00000498 ARM_enableMMU
547 00000498 E92D0003 stmfd r13!, {r0-r1}
548 0000049C EE111F10 mrc p15, #0, r1, c1, c0, #0
549 000004A0 E3A00001 mov r0,#0x0001
550 000004A4 E1811000 orr r1, r1, r0
551 000004A8 E1A00000 nop
552 000004AC E1A00000 nop
553 000004B0 EE011F10 mcr p15, #0, r1, c1, c0, #0
554 000004B4 E1A00000 nop
555 000004B8 E1A00000 nop
556 000004BC E8BD0003 ldmfd r13!, {r0-r1}
557 000004C0 E1B0F00E movs PC, R14
558 000004C4
559 000004C4 ;*******************************************************
**********
560 000004C4 ;*
561 000004C4 ;* Function Name
562 000004C4 ;* ARM_disableMMU
563 000004C4 ;* Inputs
ARM Macro Assembler Page 18
564 000004C4 ;* None
565 000004C4 ;* Outputs
566 000004C4 ;* None
567 000004C4 ;* Return Codes
568 000004C4 ;* None
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