📄 boot.lst
字号:
156 000000A4 ;* 2008-03-04
157 000000A4 ;*******************************************************
**********/
158 000000A4 SystemCtrl
159 000000A4 ;mov sp, #&01000000
160 000000A4 ;stmfd r13!, {lr}
161 000000A4
162 000000A4 ;disable all interrupt
163 000000A4 E10F1000 mrs r1, cpsr
164 000000A8 E38110C0 orr r1, r1, #0xc0
165 000000AC E121F001 msr cpsr_c, r1
ARM Macro Assembler Page 8
166 000000B0
167 000000B0 ;dll config
168 000000B0 E59F11A8 ldr r1, =&101c0e0c ;=101c0e0c(Decod
er(HOSTIF))
169 000000B4 E3A00000 mov r0, #&0
170 000000B8 E5810000 str r0, [r1,#0]
171 000000BC E59F01A0 ldr r0, =&0100300c ;fullseg loader
172 000000C0 ;ldr r0, =&0B00300c ;me
173 000000C0 E59F11A0 ldr r1, =APB_SCPLLFCTRL ;=101e0018(
SystemController(SC
PLLFCTRL))
174 000000C4 E5810000 str r0, [r1,#0]
175 000000C8 E59F019C ldr r0, =&0ffc0003
176 000000CC E59F119C ldr r1, =APB_SCPLLCTRL ;101e0014(Sy
stemController(SCPL
LCTRL))
177 000000D0 E5810000 str r0, [r1,#0]
178 000000D4 E59F1198 ldr r1, =APB_SCCTRL ;=101e0000(Syst
emController(SCCTRL
))
179 000000D8 E5910000 ldr r0, [r1,#0]
180 000000DC ;and r0, r0,#&f8 ;fullseg loader
181 000000DC E2000F7E and r0, r0,#&1f8 ;me for remapclr
182 000000E0 E3800004 orr r0, r0,#&4
183 000000E4 E3C00A07 bic r0, r0,#&7000
184 000000E8 E3800A01 orr r0, r0,#&1000
185 000000EC E3800855 orr r0, r0,#&550000
186 000000F0 E5810000 str r0, [r1,#0]
187 000000F4 wait_lock
188 000000F4 E59F0178 ldr r0, =APB_SCCTRL ;101e0000(Syste
mController(SCCTRL)
)
189 000000F8 E5900000 ldr r0, [r0,#0]
190 000000FC E2000078 and r0, r0,#&78
191 00000100 E3500020 cmp r0, #&20
192 00000104 1AFFFFFA bne wait_lock ;wait pll lock
193 00000108
194 00000108 ;smc config
195 00000108 E3A00055 mov r0, #&55
196 0000010C E59F1164 ldr r1, =SMC_DBWCR ;10100000(SMC(DB
WCR))
197 00000110 E5810000 str r0, [r1,#0]
198 00000114 E59F0160 ldr r0, =&00009999
199 00000118 E59F1160 ldr r1, =SMC_WSCR ;10100008(SMC(EDW
CR))
200 0000011C E5810000 str r0, [r1,#0]
201 00000120 E59F015C ldr r0, =&00001111
202 00000124 E59F115C ldr r1, =SMC_TAREA ;10100010(SMC(TA
REA))
203 00000128 E5810000 str r0, [r1,#0]
ARM Macro Assembler Page 9
204 0000012C E59F0150 ldr r0, =&00001111
205 00000130 E59F1154 ldr r1, =SMC_TACSR ;10100014(SMC(TA
CSR))
206 00000134 E5810000 str r0, [r1,#0]
207 00000138 E59F0144 ldr r0, =&00001111
208 0000013C E59F114C ldr r1, =SMC_TCOSR ;10100018(SMC(TC
OSR))
209 00000140 E5810000 str r0, [r1,#0]
210 00000144 E59F0138 ldr r0, =&00001111
211 00000148 E59F1144 ldr r1, =SMC_TCOHR ;1010001c(SMC(TC
OHR))
212 0000014C E5810000 str r0, [r1,#0]
213 00000150 E59F111C ldr r1, =APB_SCCTRL ;101e0000(Syste
mController(SCCTRL)
)
214 00000154 E5910000 ldr r0, [r1,#0]
215 00000158 E3800C01 orr r0, r0,#&100 ;clr memory remap
216 0000015C E5810000 str r0, [r1,#0]
217 00000160 E59F0130 ldr r0, =&000186a0
218 00000164 delay
219 00000164 E2400001 sub r0, r0,#&1
220 00000168 E3500000 cmp r0, #&0
221 0000016C 1AFFFFFC bne delay ;loop wait 100000 t
imes
222 00000170
223 00000170 ;mov r0, #&2
224 00000170 ;ldr r1, &3000031c ;101e3028 timer4setup
225 00000170 ;str r0, [r1,#0]
226 00000170 ;mov r0, #&2
227 00000170 ;ldr r1, &3000031c
228 00000170 ;str r0, [r1,#0]
229 00000170 ;mov r0, #&2
230 00000170 ;ldr r1, &3000031c
231 00000170 ;str r0, [r1,#0]
232 00000170 ;mov r0, #&82
233 00000170 ;ldr r1, &3000031c
234 00000170 ;str r0, [r1,#0]
235 00000170 E59F0124 ldr r0, =&f73bf084
236 00000174 E59F1124 ldr r1, =APB_SCPERCTRL0 ;101e001c(S
ystemController(SCP
ERCTRL0))
ARM Macro Assembler Page 10
237 00000178 E5810000 str r0, [r1,#0]
238 0000017C E59F0120 ldr r0, =&f7e2f7cf
239 00000180 E59F1120 ldr r1, =APB_SCPEREN ;101e0024(Syst
emController(SCPERE
N))
240 00000184 E5810000 str r0, [r1,#0]
241 00000188 ;ldmfd r13!, {pc}
242 00000188 E1A0F00E mov pc, lr
243 0000018C
244 0000018C
245 0000018C
246 0000018C
247 0000018C ;*******************************************************
**********
248 0000018C ;*
249 0000018C ;* Function Name
250 0000018C ;* InitStack
251 0000018C ;* Inputs
252 0000018C ;* None
253 0000018C ;* Outputs
254 0000018C ;* None
255 0000018C ;* Return Codes
256 0000018C ;* None
257 0000018C ;* Description
258 0000018C ;* This funtion init the system stack
259 0000018C ;* Date:
260 0000018C ;* 2008-03-04
261 0000018C ;*******************************************************
**********/
262 0000018C InitStack
263 0000018C E1A0000E MOV R0, LR
264 00000190
265 00000190 ;set the stack of supervisor mode
266 00000190 E321F0D3 MSR CPSR_c, #0xd3
267 00000194 E59FD0AC LDR SP, StackSvc
268 00000198 ;;set the stack of irq mode
269 00000198 E321F0D2 MSR CPSR_c, #0xd2
270 0000019C E59FD0A8 LDR SP, StackIrq
271 000001A0 ;;set the stack of fiq mode
272 000001A0 E321F0D1 MSR CPSR_c, #0xd1
273 000001A4 E59FD0A4 LDR SP, StackFiq
274 000001A8 ;;set the stack of abort mode
275 000001A8 E321F0D7 MSR CPSR_c, #0xd7
276 000001AC E59FD0A0 LDR SP, StackAbt
277 000001B0 ;;set the stack of undefined mode
278 000001B0 E321F0DB MSR CPSR_c, #0xdb
279 000001B4 E59FD09C LDR SP, StackUnd
280 000001B8 ;;set the stack of system mode
281 000001B8 E321F0DF MSR CPSR_c, #0xdf
282 000001BC ;LDR SP, =StackUsr
283 000001BC E59FD0E8 LDR SP, =||Image$$ARM_LIB_STACK$$ZI
$$Limit||
284 000001C0
285 000001C0 E1A0F000 MOV PC, R0
286 000001C4
ARM Macro Assembler Page 11
287 000001C4
288 000001C4 ;*******************************************************
**********
289 000001C4 ;*
290 000001C4 ;* Function Name
291 000001C4 ;* CopyIntVector
292 000001C4 ;* Inputs
293 000001C4 ;* None
294 000001C4 ;* Outputs
295 000001C4 ;* None
296 000001C4 ;* Return Codes
297 000001C4 ;* None
298 000001C4 ;* Description
299 000001C4 ;* This funtion copy Interrupt vector
300 000001C4 ;* Date:
301 000001C4 ;* 2008-03-04
302 000001C4 ;*******************************************************
**********/
303 000001C4 CopyIntVector
304 000001C4 E3A00000 mov r0, #&0
305 000001C8 E59F10E0 ldr r1, =Reset
306 000001CC E5912004 ldr r2, [r1,#4]
307 000001D0 E5802004 str r2, [r0,#4] ;undef_vector
308 000001D4 E5912024 ldr r2, [r1,#36]
309 000001D8 E5802024 str r2, [r0,#36]
310 000001DC E5912008 ldr r2, [r1,#8]
311 000001E0 E5802008 str r2, [r0,#8] ;swi_vector
312 000001E4 E5912028 ldr r2, [r1,#40]
313 000001E8 E5802028 str r2, [r0,#40]
314 000001EC E5912018 ldr r2, [r1,#24] ;irq_vector
315 000001F0 E5802018 str r2, [r0,#24]
316 000001F4 E5912038 ldr r2, [r1,#56]
317 000001F8 E5802038 str r2, [r0,#56]
318 000001FC E591201C ldr r2, [r1,#28] ;firq_vector
319 00000200 E580201C str r2, [r0,#28]
320 00000204 E591203C ldr r2, [r1,#60]
321 00000208 E580203C str r2, [r0,#60]
322 0000020C E591200C ldr r2, [r1,#12] ;pref_abort_vector
323 00000210 E580200C str r2, [r0,#12]
324 00000214 E591202C ldr r2, [r1,#44]
325 00000218 E580202C str r2, [r0,#44]
326 0000021C E5912010 ldr r2, [r1,#16] ;data_abort_vector
327 00000220 E5802010 str r2, [r0,#16]
328 00000224 E5912030 ldr r2, [r1,#48]
329 00000228 E5802030 str r2, [r0,#48]
330 0000022C E3A00000 mov r0, #&0
331 00000230 E59F1078 ldr r1, =Reset
332 00000234 E5912000 ldr r2, [r1,#0]
333 00000238 E5802000 str r2, [r0,#0] ;reset_vector
334 0000023C E59F2070 ldr r2, =WarmReset
335 00000240 E5802020 str r2, [r0,#32] ;reset_address
336 00000244 E1A0F00E mov pc, lr
ARM Macro Assembler Page 12
337 00000248
338 00000248
339 00000248
340 00000248
341 00000248
342 00000248
343 00000248 0000007C
StackSvc
DCD SvcStackSpace + (SVC_STACK_LEGT
H - 1)* 4
344 0000024C 00003FFC
StackIrq
DCD IrqStackSpace + (IRQ_STACK_LEGT
H - 1)* 4
345 00000250 FFFFFFFC
StackFiq
DCD FiqStackSpace + (FIQ_STACK_LEGT
H - 1)* 4
346 00000254 FFFFFFFC
StackAbt
DCD AbtStackSpace + (ABT_STACK_LEGT
H - 1)* 4
347 00000258 FFFFFFFC
StackUnd
DCD UndtStackSpace + (UND_STACK_LEG
TH - 1)* 4
348 0000025C
349 0000025C 10140000
101C0E0C
0100300C
101E0018
0FFC0003
101E0014
101E0000
10100000
00009999
10100008
00001111
10100010
10100014
10100018
1010001C
000186A0
F73BF084
101E001C
F7E2F7CF
101E0024
00000000
00000000
00000000 AREA MyStacks, DATA, NOINIT, ALIGN=4
350 00000000 SvcStackSpace
SPACE SVC_STACK_LEGTH * 4 ;the memory
of svc mode
351 00000080 IrqStackSpace
SPACE IRQ_STACK_LEGTH * 4 ;the memory
of irq mode
352 00004080 FiqStackSpace
SPACE FIQ_STACK_LEGTH * 4 ;the memory
of fiq mode
ARM Macro Assembler Page 13
353 00004080 AbtStackSpace
SPACE ABT_STACK_LEGTH * 4 ;the memory
of abort mode
354 00004080 UndtStackSpace
SPACE UND_STACK_LEGTH * 4 ;the memory
of undefined mode
355 00004080
356 00004080
357 00004080 END
Command Line: --debug --liston --dwarf2 --brief_diagnostics --keep --xref --dia
g_style=ide --cpu=ARM926EJ-S --depend=E:\RTOS\test_arm926\armtest_Debug_boot.s_
dependency_information.txt -oE:\RTOS\test_arm926\armtest_Data\Debug\ObjectCode\
boot.o -IE:\RTOS\test_arm926 -IE:\RTOS\test_arm926\main -IE:\RTOS\test_arm926\i
nclude -IE:\RTOS\test_arm926\vic -IE:\RTOS\test_arm926\ucos_source -IE:\RTOS\te
st_arm926\ucos_include -IE:\RTOS\test_arm926\ucos_cpu --predefine="RTOS_NONE SE
TA 1" E:\RTOS\test_arm926\main\boot.s
ARM Macro Assembler Page 1 Alphabetic symbol ordering
Relocatable symbols
CopyIntVector 000001C4
Symbol: CopyIntVector
Definitions
At line 303 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 137 in file E:\RTOS\test_arm926\main\boot.s
Comment: CopyIntVector used once
DataAbort 0000004C
Symbol: DataAbort
Definitions
At line 92 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 70 in file E:\RTOS\test_arm926\main\boot.s
At line 93 in file E:\RTOS\test_arm926\main\boot.s
DataAbortAddr 00000030
Symbol: DataAbortAddr
Definitions
At line 70 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 60 in file E:\RTOS\test_arm926\main\boot.s
Comment: DataAbortAddr used once
FIQ_Addr 0000003C
Symbol: FIQ_Addr
Definitions
At line 74 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 63 in file E:\RTOS\test_arm926\main\boot.s
Comment: FIQ_Addr used once
IRQ_Addr 00000038
Symbol: IRQ_Addr
Definitions
At line 73 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 62 in file E:\RTOS\test_arm926\main\boot.s
Comment: IRQ_Addr used once
InitStack 0000018C
Symbol: InitStack
Definitions
At line 262 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 135 in file E:\RTOS\test_arm926\main\boot.s
Comment: InitStack used once
Nouse 00000034
Symbol: Nouse
Definitions
At line 71 in file E:\RTOS\test_arm926\main\boot.s
Uses
None
Comment: Nouse unused
PrefetchAbort 00000048
ARM Macro Assembler Page 2 Alphabetic symbol ordering
Relocatable symbols
Symbol: PrefetchAbort
Definitions
At line 88 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 69 in file E:\RTOS\test_arm926\main\boot.s
At line 89 in file E:\RTOS\test_arm926\main\boot.s
PrefetchAddr 0000002C
Symbol: PrefetchAddr
Definitions
At line 69 in file E:\RTOS\test_arm926\main\boot.s
Uses
At line 59 in file E:\RTOS\test_arm926\main\boot.s
Comment: PrefetchAddr used once
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