pxa27x.h

周立功PXA270教学实验箱的ARM汇编指令实验2

#define UDCDRU          (*((volatile unsigned long *) 0x40600350)) /* Data Register - EPU */
#define UDCDRV          (*((volatile unsigned long *) 0x40600354)) /* Data Register - EPV */
#define UDCDRW          (*((volatile unsigned long *) 0x40600358)) /* Data Register - EPW */
#define UDCDRX          (*((volatile unsigned long *) 0x4060035C)) /* Data Register - EPX */

#define UDCCN(x)       	(*((volatile unsigned long *) (0x40600400 + ((x) << 2)) )) 
#define UDCCRA          (*((volatile unsigned long *) 0x40600404)) /* Configuration register EPA */
#define UDCCRB          (*((volatile unsigned long *) 0x40600408)) /* Configuration register EPB */
#define UDCCRC          (*((volatile unsigned long *) 0x4060040C)) /* Configuration register EPC */
#define UDCCRD          (*((volatile unsigned long *) 0x40600410)) /* Configuration register EPD */
#define UDCCRE          (*((volatile unsigned long *) 0x40600414)) /* Configuration register EPE */
#define UDCCRF          (*((volatile unsigned long *) 0x40600418)) /* Configuration register EPF */
#define UDCCRG          (*((volatile unsigned long *) 0x4060041C)) /* Configuration register EPG */
#define UDCCRH          (*((volatile unsigned long *) 0x40600420)) /* Configuration register EPH */
#define UDCCRI          (*((volatile unsigned long *) 0x40600424)) /* Configuration register EPI */
#define UDCCRJ          (*((volatile unsigned long *) 0x40600428)) /* Configuration register EPJ */
#define UDCCRK          (*((volatile unsigned long *) 0x4060042C)) /* Configuration register EPK */
#define UDCCRL          (*((volatile unsigned long *) 0x40600430)) /* Configuration register EPL */
#define UDCCRM          (*((volatile unsigned long *) 0x40600434)) /* Configuration register EPM */
#define UDCCRN          (*((volatile unsigned long *) 0x40600438)) /* Configuration register EPN */
#define UDCCRP          (*((volatile unsigned long *) 0x4060043C)) /* Configuration register EPP */
#define UDCCRQ          (*((volatile unsigned long *) 0x40600440)) /* Configuration register EPQ */
#define UDCCRR          (*((volatile unsigned long *) 0x40600444)) /* Configuration register EPR */
#define UDCCRS          (*((volatile unsigned long *) 0x40600448)) /* Configuration register EPS */
#define UDCCRT          (*((volatile unsigned long *) 0x4060044C)) /* Configuration register EPT */
#define UDCCRU          (*((volatile unsigned long *) 0x40600450)) /* Configuration register EPU */
#define UDCCRV          (*((volatile unsigned long *) 0x40600454)) /* Configuration register EPV */
#define UDCCRW          (*((volatile unsigned long *) 0x40600458)) /* Configuration register EPW */
#define UDCCRX          (*((volatile unsigned long *) 0x4060045C)) /* Configuration register EPX */

#define UDCCONR_CN		(0x03 << 25)	/* Configuration Number */
#define UDCCONR_CN_S	(25)
#define UDCCONR_IN		(0x07 << 22)	/* Interface Number */
#define UDCCONR_IN_S	(22)
#define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
#define UDCCONR_AISN_S	(19)
#define UDCCONR_EN		(0x0f << 15)	/* Endpoint Number */
#define UDCCONR_EN_S	(15)
#define UDCCONR_ET		(0x03 << 13)	/* Endpoint Type: */
#define UDCCONR_ET_S	(13)
#define UDCCONR_ET_INT	(0x03 << 13)	/*   Interrupt */
#define UDCCONR_ET_BULK	(0x02 << 13)	/*   Bulk */
#define UDCCONR_ET_ISO	(0x01 << 13)	/*   Isochronous */
#define UDCCONR_ET_NU	(0x00 << 13)	/*   Not used */
#define UDCCONR_ED		(1 << 12)		/* Endpoint Direction */
#define UDCCONR_MPS		(0x3ff << 2)	/* Maximum Packet Size */
#define UDCCONR_MPS_S	(2)
#define UDCCONR_DE		(1 << 1)		/* Double Buffering Enable */
#define UDCCONR_EE		(1 << 0)		/* Endpoint Enable */

#define UDC_INT_FIFOERROR  	(0x2)
#define UDC_INT_PACKETCMP  	(0x1)

#define UDC_FNR_MASK     	(0x7ff)

#define UDCCSR_WR_MASK   	(UDCCSR_DME|UDCCSR_FST)
#define UDC_BCR_MASK    	(0x3ff)


/*
* Fast Infrared Communication Port
*/
#define ICCR0		(*((volatile unsigned long *) 0x40800000))  /* ICP Control Register 0 */
#define ICCR1		(*((volatile unsigned long *) 0x40800004))  /* ICP Control Register 1 */
#define ICCR2		(*((volatile unsigned long *) 0x40800008))  /* ICP Control Register 2 */
#define ICDR		(*((volatile unsigned long *) 0x4080000c))  /* ICP Data Register */
#define ICSR0		(*((volatile unsigned long *) 0x40800014))  /* ICP Status Register 0 */
#define ICSR1		(*((volatile unsigned long *) 0x40800018))  /* ICP Status Register 1 */

#define ICCR0_AME	(1 << 7)	/* Adress match enable */
#define ICCR0_TIE	(1 << 6)	/* Transmit FIFO interrupt enable */
#define ICCR0_RIE	(1 << 5)	/* Recieve FIFO interrupt enable */
#define ICCR0_RXE	(1 << 4)	/* Receive enable */
#define ICCR0_TXE	(1 << 3)	/* Transmit enable */
#define ICCR0_TUS	(1 << 2)	/* Transmit FIFO underrun select */
#define ICCR0_LBM	(1 << 1)	/* Loopback mode */
#define ICCR0_ITR	(1 << 0)	/* IrDA transmission */


#define ICCR2_RXP       (1 << 3)	/* Receive Pin Polarity select */
#define ICCR2_TXP       (1 << 2)	/* Transmit Pin Polarity select */
#define ICCR2_TRIG		(3 << 0)	/* Receive FIFO Trigger threshold */
#define ICCR2_TRIG_8    (0 << 0)	/* 	>= 8 bytes */
#define ICCR2_TRIG_16   (1 << 0)	/*	>= 16 bytes */
#define ICCR2_TRIG_32   (2 << 0)	/*	>= 32 bytes */

#define ICSR0_EOC	(1 << 6)	/* DMA End of Descriptor Chain */
#define ICSR0_FRE	(1 << 5)	/* Framing error */
#define ICSR0_RFS	(1 << 4)	/* Receive FIFO service request */
#define ICSR0_TFS	(1 << 3)	/* Transnit FIFO service request */
#define ICSR0_RAB	(1 << 2)	/* Receiver abort */
#define ICSR0_TUR	(1 << 1)	/* Trunsmit FIFO underun */
#define ICSR0_EIF	(1 << 0)	/* End/Error in FIFO */

#define ICSR1_ROR	(1 << 6)	/* Receiver FIFO underrun  */
#define ICSR1_CRE	(1 << 5)	/* CRC error */
#define ICSR1_EOF	(1 << 4)	/* End of frame */
#define ICSR1_TNF	(1 << 3)	/* Transmit FIFO not full */
#define ICSR1_RNE	(1 << 2)	/* Receive FIFO not empty */
#define ICSR1_TBY	(1 << 1)	/* Tramsmiter busy flag */
#define ICSR1_RSY	(1 << 0)	/* Recevier synchronized flag */


/*
* Real Time Clock
*/
#define RCNR		(*((volatile unsigned long *) 0x40900000))  /* RTC Count Register */
#define RTAR		(*((volatile unsigned long *) 0x40900004))  /* RTC Alarm Register */
#define RTSR		(*((volatile unsigned long *) 0x40900008))  /* RTC Status Register */
#define RTTR		(*((volatile unsigned long *) 0x4090000C))  /* RTC Timer Trim Register */
#define RTCPICR     (*((volatile unsigned long *) 0x40900034))	/* Periodic Interrupt Counter Register */
#define PIAR		(*((volatile unsigned long *) 0x40900038))  /* Periodic Interrupt Alarm Register */

#define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
#define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */

#define  RDCR        (*((volatile unsigned long *) 0x40900010))		/* RTC Day Counter Register */
#define  RYCR        (*((volatile unsigned long *) 0x40900014))		/* RTC Year Counter Register */
#define  RDAR1       (*((volatile unsigned long *) 0x40900018))		/* RTC Wristwatch Day Alarm Register 1 */
#define  RYAR1       (*((volatile unsigned long *) 0x4090001C))		/* RTC Wristwatch Year Alarm Register 1 */
#define  RDAR2       (*((volatile unsigned long *) 0x40900020))		/* RTC Wristwatch Day Alarm Register 2 */
#define  RYAR2       (*((volatile unsigned long *) 0x40900024))		/* RTC Wristwatch Year Alarm Register 2 */

#define  SWCR        (*((volatile unsigned long *) 0x40900028))		/* RTC Stopwath Counter Register */
#define  SWAR1       (*((volatile unsigned long *) 0x4090002C))		/* RTC Stopwath Alarm Register 1 */
#define  SWAR2       (*((volatile unsigned long *) 0x40900030))		/* RTC Stopwath Alarm Register 2 */


/*
* OS Timer & Match Registers
*/
#define OSMR0		(*((volatile unsigned long *) 0x40A00000))  /* OS Timer Match 0 Register */
#define OSMR1		(*((volatile unsigned long *) 0x40A00004))  /* OS Timer Match 1 Register */
#define OSMR2		(*((volatile unsigned long *) 0x40A00008))  /* OS Timer Match 2 Register */
#define OSMR3		(*((volatile unsigned long *) 0x40A0000C))  /* OS Timer Match 3 Register */
#define OSMR4		(*((volatile unsigned long *) 0x40A00080))  /* OS Timer Match 4 Register */
#define OSMR5		(*((volatile unsigned long *) 0x40A00084))  /* OS Timer Match 5 Register */
#define OSMR6		(*((volatile unsigned long *) 0x40A00088))  /* OS Timer Match 6 Register */
#define OSMR7		(*((volatile unsigned long *) 0x40A0008c))  /* OS Timer Match 7 Register */
#define OSMR8		(*((volatile unsigned long *) 0x40A00090))  /* OS Timer Match 8 Register */
#define OSMR9		(*((volatile unsigned long *) 0x40A00094))  /* OS Timer Match 9 Register */
#define OSMR10		(*((volatile unsigned long *) 0x40A00098))  /* OS Timer Match 10 Register */
#define OSMR11		(*((volatile unsigned long *) 0x40A0009c))  /* OS Timer Match 11 Register */

#define OSCR0		(*((volatile unsigned long *) 0x40A00010))  /* OS Timer Counter 0 Register */
#define OSCR4		(*((volatile unsigned long *) 0x40A00044))  /* OS Timer Counter 4 Register */
#define OSCR5		(*((volatile unsigned long *) 0x40A00048))  /* OS Timer Counter 5 Register */
#define OSCR6		(*((volatile unsigned long *) 0x40A0004c))  /* OS Timer Counter 6 Register */
#define OSCR7		(*((volatile unsigned long *) 0x40A00040))  /* OS Timer Counter 7 Register */
#define OSCR8		(*((volatile unsigned long *) 0x40A00050))  /* OS Timer Counter 8 Register */
#define OSCR9		(*((volatile unsigned long *) 0x40A00054))  /* OS Timer Counter 9 Register */
#define OSCR10		(*((volatile unsigned long *) 0x40A00058))  /* OS Timer Counter 10 Register */
#define OSCR11		(*((volatile unsigned long *) 0x40A0005c))  /* OS Timer Counter 11 Register */

#define OMCR4		(*((volatile unsigned long *) 0x40A000C0))  /* OS Timer Match Control 4 Register */
#define OMCR5		(*((volatile unsigned long *) 0x40A000C4))  /* OS Timer Match Control 5 Register */
#define OMCR6		(*((volatile unsigned long *) 0x40A000C8))  /* OS Timer Match Control 6 Register */
#define OMCR7		(*((volatile unsigned long *) 0x40A000CC))  /* OS Timer Match Control 7 Register */
#define OMCR8		(*((volatile unsigned long *) 0x40A000D0))  /* OS Timer Match Control 8 Register */
#define OMCR9		(*((volatile unsigned long *) 0x40A000D4))  /* OS Timer Match Control 9 Register */
#define OMCR10		(*((volatile unsigned long *) 0x40A000D8))  /* OS Timer Match Control 10 Register */
#define OMCR11		(*((volatile unsigned long *) 0x40A000DC))  /* OS Timer Match Control 11 Register */

#define OSSR		(*((volatile unsigned long *) 0x40A00014))  /* OS Timer Status Register */
#define OWER		(*((volatile unsigned long *) 0x40A00018))  /* OS Timer Watchdog Enable Register */
#define OIER		(*((volatile unsigned long *) 0x40A0001C))  /* OS Timer Interrupt Enable Register */
#define OSNR		(*((volatile unsigned long *) 0x40A00020))  /* OS Timer Snapshot Register */

#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
#define OSSR_M0		(1 << 0)	/* Match status channel 0 */

#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */

#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
#def