📄 pxa27x.h
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#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
#define CAR (*((volatile unsigned long *) 0x40500020)) /* CODEC Access Register */
#define CAR_CAIP (1 << 0) /* Codec Access In Progress */
#define PCDR (*((volatile unsigned long *) 0x40500040)) /* PCM FIFO Data Register */
#define MCDR (*((volatile unsigned long *) 0x40500060)) /* Mic-in FIFO Data Register */
#define MOCR (*((volatile unsigned long *) 0x40500100)) /* Modem Out Control Register */
#define MOCR_FEIE (1 << 3) /* FIFO Error */
#define MICR (*((volatile unsigned long *) 0x40500108)) /* Modem In Control Register */
#define MICR_FEIE (1 << 3) /* FIFO Error */
#define MOSR (*((volatile unsigned long *) 0x40500110)) /* Modem Out Status Register */
#define MOSR_FIFOE (1 << 4) /* FIFO error */
#define MISR (*((volatile unsigned long *) 0x40500118)) /* Modem In Status Register */
#define MISR_FIFOE (1 << 4) /* FIFO error */
#define MODR (*((volatile unsigned long *) 0x40500140)) /* Modem FIFO Data Register */
#define PAC_REG_BASE (*((volatile unsigned long *)(0x40500200) /* Primary Audio Codec */
#define SAC_REG_BASE (*((volatile unsigned long *)(0x40500300) /* Secondary Audio Codec */
#define PMC_REG_BASE (*((volatile unsigned long *)(0x40500400) /* Primary Modem Codec */
#define SMC_REG_BASE (*((volatile unsigned long *)(0x40500500) /* Secondary Modem Codec */
/*
* USB Device Controller
*/
#define UDCCR (*((volatile unsigned long *) 0x40600000)) /* UDC Control Register */
#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */
#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */
#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */
#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
#define UDCCR_ACN (0x03 << 11)/* Active UDC configuration Number */
#define UDCCR_ACN_S 11
#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
#define UDCCR_AIN_S 8
#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */
#define UDCCR_AAISN_S 5
#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */
#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */
#define UDCCR_UDR (1 << 2) /* UDC Resume */
#define UDCCR_UDA (1 << 1) /* UDC Active */
#define UDCCR_UDE (1 << 0) /* UDC Enable */
#define UDCICR0 (*((volatile unsigned long *) 0x40600004)) /* UDC Interrupt Control Register0 */
#define UDCICR1 (*((volatile unsigned long *) 0x40600008)) /* UDC Interrupt Control Register1 */
#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
#define UDC_INT_FIFOERROR (0x2)
#define UDC_INT_PACKETCMP (0x1)
#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR0 (*((volatile unsigned long *) 0x4060000C)) /* UDC Interrupt Status Register 0 */
#define UDCISR1 (*((volatile unsigned long *) 0x40600010)) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCFNR (*((volatile unsigned long *) 0x40600014)) /* UDC Frame Number Register */
#define UDCOTGICR (*((volatile unsigned long *) 0x40600018)) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */
#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */
#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */
#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */
#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */
#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */
#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
#define UDCCSN(x) (*((volatile unsigned long *) (0x40600100 + ((x) << 2)) ))
#define UDCCSR0 (*((volatile unsigned long *) 0x40600100)) /* UDC Control/Status register - Endpoint 0 */
#define UDCCSR0_SA (1 << 7) /* Setup Active */
#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
#define UDCCSR0_FST (1 << 5) /* Force Stall */
#define UDCCSR0_SST (1 << 4) /* Sent Stall */
#define UDCCSR0_DME (1 << 3) /* DMA Enable */
#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
#define UDCCSRA (*((volatile unsigned long *) 0x40600104)) /* UDC Control/Status register - Endpoint A */
#define UDCCSRB (*((volatile unsigned long *) 0x40600108)) /* UDC Control/Status register - Endpoint B */
#define UDCCSRC (*((volatile unsigned long *) 0x4060010C)) /* UDC Control/Status register - Endpoint C */
#define UDCCSRD (*((volatile unsigned long *) 0x40600110)) /* UDC Control/Status register - Endpoint D */
#define UDCCSRE (*((volatile unsigned long *) 0x40600114)) /* UDC Control/Status register - Endpoint E */
#define UDCCSRF (*((volatile unsigned long *) 0x40600118)) /* UDC Control/Status register - Endpoint F */
#define UDCCSRG (*((volatile unsigned long *) 0x4060011C)) /* UDC Control/Status register - Endpoint G */
#define UDCCSRH (*((volatile unsigned long *) 0x40600120)) /* UDC Control/Status register - Endpoint H */
#define UDCCSRI (*((volatile unsigned long *) 0x40600124)) /* UDC Control/Status register - Endpoint I */
#define UDCCSRJ (*((volatile unsigned long *) 0x40600128)) /* UDC Control/Status register - Endpoint J */
#define UDCCSRK (*((volatile unsigned long *) 0x4060012C)) /* UDC Control/Status register - Endpoint K */
#define UDCCSRL (*((volatile unsigned long *) 0x40600130)) /* UDC Control/Status register - Endpoint L */
#define UDCCSRM (*((volatile unsigned long *) 0x40600134)) /* UDC Control/Status register - Endpoint M */
#define UDCCSRN (*((volatile unsigned long *) 0x40600138)) /* UDC Control/Status register - Endpoint N */
#define UDCCSRP (*((volatile unsigned long *) 0x4060013C)) /* UDC Control/Status register - Endpoint P */
#define UDCCSRQ (*((volatile unsigned long *) 0x40600140)) /* UDC Control/Status register - Endpoint Q */
#define UDCCSRR (*((volatile unsigned long *) 0x40600144)) /* UDC Control/Status register - Endpoint R */
#define UDCCSRS (*((volatile unsigned long *) 0x40600148)) /* UDC Control/Status register - Endpoint S */
#define UDCCSRT (*((volatile unsigned long *) 0x4060014C)) /* UDC Control/Status register - Endpoint T */
#define UDCCSRU (*((volatile unsigned long *) 0x40600150)) /* UDC Control/Status register - Endpoint U */
#define UDCCSRV (*((volatile unsigned long *) 0x40600154)) /* UDC Control/Status register - Endpoint V */
#define UDCCSRW (*((volatile unsigned long *) 0x40600158)) /* UDC Control/Status register - Endpoint W */
#define UDCCSRX (*((volatile unsigned long *) 0x4060015C)) /* UDC Control/Status register - Endpoint X */
#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
#define UDCCSR_FST (1 << 5) /* Force STALL */
#define UDCCSR_SST (1 << 4) /* Sent STALL */
#define UDCCSR_DME (1 << 3) /* DMA Enable */
#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
#define UDCCSR_PC (1 << 1) /* Packet Complete */
#define UDCCSR_FS (1 << 0) /* FIFO needs service */
#define UDCBCN(x) (*((volatile unsigned long *) (0x40600200 + ((x) << 2)) ))
#define UDCBCR0 (*((volatile unsigned long *) 0x40600200)) /* Byte Count Register - EP0 */
#define UDCBCRA (*((volatile unsigned long *) 0x40600204)) /* Byte Count Register - EPA */
#define UDCBCRB (*((volatile unsigned long *) 0x40600208)) /* Byte Count Register - EPB */
#define UDCBCRC (*((volatile unsigned long *) 0x4060020C)) /* Byte Count Register - EPC */
#define UDCBCRD (*((volatile unsigned long *) 0x40600210)) /* Byte Count Register - EPD */
#define UDCBCRE (*((volatile unsigned long *) 0x40600214)) /* Byte Count Register - EPE */
#define UDCBCRF (*((volatile unsigned long *) 0x40600218)) /* Byte Count Register - EPF */
#define UDCBCRG (*((volatile unsigned long *) 0x4060021C)) /* Byte Count Register - EPG */
#define UDCBCRH (*((volatile unsigned long *) 0x40600220)) /* Byte Count Register - EPH */
#define UDCBCRI (*((volatile unsigned long *) 0x40600224)) /* Byte Count Register - EPI */
#define UDCBCRJ (*((volatile unsigned long *) 0x40600228)) /* Byte Count Register - EPJ */
#define UDCBCRK (*((volatile unsigned long *) 0x4060022C)) /* Byte Count Register - EPK */
#define UDCBCRL (*((volatile unsigned long *) 0x40600230)) /* Byte Count Register - EPL */
#define UDCBCRM (*((volatile unsigned long *) 0x40600234)) /* Byte Count Register - EPM */
#define UDCBCRN (*((volatile unsigned long *) 0x40600238)) /* Byte Count Register - EPN */
#define UDCBCRP (*((volatile unsigned long *) 0x4060023C)) /* Byte Count Register - EPP */
#define UDCBCRQ (*((volatile unsigned long *) 0x40600240)) /* Byte Count Register - EPQ */
#define UDCBCRR (*((volatile unsigned long *) 0x40600244)) /* Byte Count Register - EPR */
#define UDCBCRS (*((volatile unsigned long *) 0x40600248)) /* Byte Count Register - EPS */
#define UDCBCRT (*((volatile unsigned long *) 0x4060024C)) /* Byte Count Register - EPT */
#define UDCBCRU (*((volatile unsigned long *) 0x40600250)) /* Byte Count Register - EPU */
#define UDCBCRV (*((volatile unsigned long *) 0x40600254)) /* Byte Count Register - EPV */
#define UDCBCRW (*((volatile unsigned long *) 0x40600258)) /* Byte Count Register - EPW */
#define UDCBCRX (*((volatile unsigned long *) 0x4060025C)) /* Byte Count Register - EPX */
#define UDCDN(x) (*((volatile unsigned long *) (0x40600300 + ((x) << 2)) ))
#define UDCDR0 (*((volatile unsigned long *) 0x40600300)) /* Data Register - EP0 */
#define UDCDRA (*((volatile unsigned long *) 0x40600304)) /* Data Register - EPA */
#define UDCDRB (*((volatile unsigned long *) 0x40600308)) /* Data Register - EPB */
#define UDCDRC (*((volatile unsigned long *) 0x4060030C)) /* Data Register - EPC */
#define UDCDRD (*((volatile unsigned long *) 0x40600310)) /* Data Register - EPD */
#define UDCDRE (*((volatile unsigned long *) 0x40600314)) /* Data Register - EPE */
#define UDCDRF (*((volatile unsigned long *) 0x40600318)) /* Data Register - EPF */
#define UDCDRG (*((volatile unsigned long *) 0x4060031C)) /* Data Register - EPG */
#define UDCDRH (*((volatile unsigned long *) 0x40600320)) /* Data Register - EPH */
#define UDCDRI (*((volatile unsigned long *) 0x40600324)) /* Data Register - EPI */
#define UDCDRJ (*((volatile unsigned long *) 0x40600328)) /* Data Register - EPJ */
#define UDCDRK (*((volatile unsigned long *) 0x4060032C)) /* Data Register - EPK */
#define UDCDRL (*((volatile unsigned long *) 0x40600330)) /* Data Register - EPL */
#define UDCDRM (*((volatile unsigned long *) 0x40600334)) /* Data Register - EPM */
#define UDCDRN (*((volatile unsigned long *) 0x40600338)) /* Data Register - EPN */
#define UDCDRP (*((volatile unsigned long *) 0x4060033C)) /* Data Register - EPP */
#define UDCDRQ (*((volatile unsigned long *) 0x40600340)) /* Data Register - EPQ */
#define UDCDRR (*((volatile unsigned long *) 0x40600344)) /* Data Register - EPR */
#define UDCDRS (*((volatile unsigned long *) 0x40600348)) /* Data Register - EPS */
#define UDCDRT (*((volatile unsigned long *) 0x4060034C)) /* Data Register - EPT */
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