pxa27x.h

周立功PXA270教学实验箱的ARM汇编指令实验2

#define STMSR		(*((volatile unsigned long *) 0x40700018))  /* Reserved */
#define STSPR		(*((volatile unsigned long *) 0x4070001C))  /* Scratch Pad Register (read/write) */
#define STISR		(*((volatile unsigned long *) 0x40700020))  /* Infrared Selection Register (read/write) */
#define STDLL		(*((volatile unsigned long *) 0x40700000))  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH		(*((volatile unsigned long *) 0x40700004))  /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define STFOR    	(*((volatile unsigned char *) 0x40700024))	/* Receive FIFO Occupancy Register */
#define STABR    	(*((volatile unsigned char *) 0x40700028))	/* Auto-Baud control Register */
#define STACR    	(*((volatile unsigned char *) 0x4070002C))	/* Auto-baud Count Register */


#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
#define IER_UUE		(1 << 6)	/* UART Unit Enable */
#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */

#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
#define IIR_TOD		(1 << 3)	/* Time Out Detected */
#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */

#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
#define FCR_ITL_1	(0)
#define FCR_ITL_8	(FCR_ITL1)
#define FCR_ITL_16	(FCR_ITL2)
#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)

#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
#define LCR_SB		(1 << 6)	/* Set Break */
#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
#define LCR_EPS		(1 << 4)	/* Even Parity Select */
#define LCR_PEN		(1 << 3)	/* Parity Enable */
#define LCR_STB		(1 << 2)	/* Stop Bit */
#define LCR_WLS1	(1 << 1)	/* Word Length Select */
#define LCR_WLS0	(1 << 0)	/* Word Length Select */

#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
#define LSR_BI		(1 << 4)	/* Break Interrupt */
#define LSR_FE		(1 << 3)	/* Framing Error */
#define LSR_PE		(1 << 2)	/* Parity Error */
#define LSR_OE		(1 << 1)	/* Overrun Error */
#define LSR_DR		(1 << 0)	/* Data Ready */

#define MCR_LOOP	(1 << 4)
#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
#define MCR_RTS		(1 << 1)	/* Request to Send */
#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */

#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
#define MSR_RI		(1 << 6)	/* Ring Indicator */
#define MSR_DSR		(1 << 5)	/* Data Set Ready */
#define MSR_CTS		(1 << 4)	/* Clear To Send */
#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */

/*
* IrSR (Infrared Selection Register)
*/
#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */


/*
 * I2C registers
 */
#define IBMR		(*((volatile unsigned long *) 0x40301680))  /* I2C Bus Monitor Register - IBMR */
#define IDBR		(*((volatile unsigned long *) 0x40301688))  /* I2C Data Buffer Register - IDBR */
#define ICR			(*((volatile unsigned long *) 0x40301690))  /* I2C Control Register - ICR */
#define ISR			(*((volatile unsigned long *) 0x40301698))  /* I2C Status Register - ISR */
#define ISAR		(*((volatile unsigned long *) 0x403016A0))  /* I2C Slave Address Register - ISAR */

#define PWRIBMR    	(*((volatile unsigned long *) 0x40f00180))  /* Power I2C Bus Monitor Register-IBMR */
#define PWRIDBR    	(*((volatile unsigned long *) 0x40f00188))  /* Power I2C Data Buffer Register-IDBR */
#define PWRICR 		(*((volatile unsigned long *) 0x40f00190))  /* Power I2C Control Register - ICR */
#define PWRISR 		(*((volatile unsigned long *) 0x40f00198))  /* Power I2C Status Register - ISR */
#define PWRISAR    	(*((volatile unsigned long *) 0x40f001A0))  /*Power I2C Slave Address Register-ISAR */

#define ICR_START	(1 << 0)	   /* start bit */
#define ICR_STOP	(1 << 1)	   /* stop bit */
#define ICR_ACKNAK	(1 << 2)	   /* send ACK(0) or NAK(1) */
#define ICR_TB		(1 << 3)	   /* transfer byte bit */
#define ICR_MA		(1 << 4)	   /* master abort */
#define ICR_SCLE	(1 << 5)	   /* master clock enable */
#define ICR_IUE		(1 << 6)	   /* unit enable */
#define ICR_GCD		(1 << 7)	   /* general call disable */
#define ICR_ITEIE	(1 << 8)	   /* enable tx interrupts */
#define ICR_IRFIE	(1 << 9)	   /* enable rx interrupts */
#define ICR_BEIE	(1 << 10)	   /* enable bus error ints */
#define ICR_SSDIE	(1 << 11)	   /* slave STOP detected int enable */
#define ICR_ALDIE	(1 << 12)	   /* enable arbitration interrupt */
#define ICR_SADIE	(1 << 13)	   /* slave address detected int enable */
#define ICR_UR		(1 << 14)	   /* unit reset */

#define ISR_RWM		(1 << 0)	   /* read/write mode */
#define ISR_ACKNAK	(1 << 1)	   /* ack/nak status */
#define ISR_UB		(1 << 2)	   /* unit busy */
#define ISR_IBB		(1 << 3)	   /* bus busy */
#define ISR_SSD		(1 << 4)	   /* slave stop detected */
#define ISR_ALD		(1 << 5)	   /* arbitration loss detected */
#define ISR_ITE		(1 << 6)	   /* tx buffer empty */
#define ISR_IRF		(1 << 7)	   /* rx buffer full */
#define ISR_GCAD	(1 << 8)	   /* general call address detected */
#define ISR_SAD		(1 << 9)	   /* slave address detected */
#define ISR_BED		(1 << 10)	   /* bus error no ACK/NAK */


/*
* Serial Audio Controller
*/
#define SACR0		(*((volatile unsigned long *) 0x40400000))  /* Global Control Register */
#define SACR1		(*((volatile unsigned long *) 0x40400004))  /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0		(*((volatile unsigned long *) 0x4040000C))  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR		(*((volatile unsigned long *) 0x40400014))  /* Serial Audio Interrupt Mask Register */
#define SAICR		(*((volatile unsigned long *) 0x40400018))  /* Serial Audio Interrupt Clear Register */
#define SADIV		(*((volatile unsigned long *) 0x40400060))  /* Audio Clock Divider Register. */
#define SADR		(*((volatile unsigned long *) 0x40400080))  /* Serial Audio Data Register (TX and RX FIFO access Register). */


/*
* AC97 Controller registers
*/
#define POCR		(*((volatile unsigned long *) 0x40500000))  /* PCM Out Control Register */
#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */

#define PICR		(*((volatile unsigned long *) 0x40500004))  /* PCM In Control Register */
#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */

#define MCCR		(*((volatile unsigned long *) 0x40500008))  /* Mic In Control Register */
#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */

#define GCR			(*((volatile unsigned long *) 0x4050000C))  /* Global Control Register */
#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
#define GCR_GIE			(1 << 0)	/* Codec GPI Interrupt Enable */

#define POSR		(*((volatile unsigned long *) 0x40500010))  /* PCM Out Status Register */
#define POSR_FIFOE	(1 << 4)	/* FIFO error */

#define PISR		(*((volatile unsigned long *) 0x40500014))  /* PCM In Status Register */
#define PISR_FIFOE	(1 << 4)	/* FIFO error */

#define MCSR		(*((volatile unsigned long *) 0x40500018))  /* Mic In Status Register */
#define MCSR_FIFOE	(1 << 4)	/* FIFO error */

#define GSR			(*((volatile unsigned long *) 0x4050001C))  /* Global Status Register */
#define GSR_CDONE		(1 << 19)	/* Command Done */
#define GSR_SDONE		(1 << 18)	/* Status Done */
#define GSR_RDCS		(1 << 15)	/* Read Completion Status */
#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
#define GSR_SECRES		(1 << 11)	/* Secondary Resume Interrupt */
#define GSR_PRIRES		(1 << 10)	/* Primary Resume Interrupt */
#define GSR_SCR			(1 << 9)	/* Secondary Codec Ready */
#define GSR_PCR			(1 << 8)	/*  Primary Codec Ready */
#define GSR_MINT		(1 << 7)	/* Mic In Interrupt */
#define GSR_POINT		(1 << 6)	/* PCM Out Interrupt */
#define GSR_PIINT		(1 << 5)	/* PCM In Interrupt */
#define GSR_MOINT		(1 << 2)	/* Modem Out Interrupt */
#define GSR_MIINT		(1 << 1)	/* Modem In Interrupt */