pxa27x.h

周立功PXA270教学实验箱的ARM汇编指令实验2

#define DRCMR45		(*((volatile unsigned long *) 0x400001B4))  /* Request to Channel Map Register for USB endpoint V Request */
#define DRCMR46		(*((volatile unsigned long *) 0x400001B8))  /* Request to Channel Map Register for USB endpoint W Request */
#define DRCMR47		(*((volatile unsigned long *) 0x400001BC))  /* Request to Channel Map Register for USB endpoint X Request */
#define DRCMR48		(*((volatile unsigned long *) 0x400001C0))  /* Request to Channel Map Register for MSL receive Request1 */
#define DRCMR49		(*((volatile unsigned long *) 0x400001C4))  /* Request to Channel Map Register for MSL transmit Request1 */
#define DRCMR50		(*((volatile unsigned long *) 0x400001C8))  /* Request to Channel Map Register for MSL receive Request2 */
#define DRCMR51		(*((volatile unsigned long *) 0x400001CC))  /* Request to Channel Map Register for MSL transmit Request2 */
#define DRCMR52		(*((volatile unsigned long *) 0x400001D0))  /* Request to Channel Map Register for MSL receive Request3 */
#define DRCMR53		(*((volatile unsigned long *) 0x400001D4))  /* Request to Channel Map Register for MSL transmit Request3 */
#define DRCMR54		(*((volatile unsigned long *) 0x400001D8))  /* Request to Channel Map Register for MSL receive Request4 */
#define DRCMR55		(*((volatile unsigned long *) 0x400001DC))  /* Request to Channel Map Register for MSL transmit Request4 */
#define DRCMR56		(*((volatile unsigned long *) 0x400001E0))  /* Request to Channel Map Register for MSL receive Request5 */
#define DRCMR57		(*((volatile unsigned long *) 0x400001E4))  /* Request to Channel Map Register for MSL transmit Request5 */
#define DRCMR58		(*((volatile unsigned long *) 0x400001E8))  /* Request to Channel Map Register for MSL receive Request6 */
#define DRCMR59		(*((volatile unsigned long *) 0x400001EC))  /* Request to Channel Map Register for MSL transmit Request6 */
#define DRCMR60		(*((volatile unsigned long *) 0x400001F0))  /* Request to Channel Map Register for MSL receive Request7 */
#define DRCMR61		(*((volatile unsigned long *) 0x400001F4))  /* Request to Channel Map Register for MSL transmit Request7 */
#define DRCMR62		(*((volatile unsigned long *) 0x400001F8))  /* Request to Channel Map Register for USIM receive Request */
#define DRCMR63		(*((volatile unsigned long *) 0x400001FC))  /* Request to Channel Map Register for USIM transmit Request */

#define DRCMR64		(*((volatile unsigned long *) 0x40001100))  /* Request to Channel Map Register for Memory stick receive Request */
#define DRCMR65		(*((volatile unsigned long *) 0x40001104))  /* Request to Channel Map Register for Memory stick transmit Request */
#define DRCMR66		(*((volatile unsigned long *) 0x40001108))  /* Request to Channel Map Register for SSP3 receive Request */
#define DRCMR67		(*((volatile unsigned long *) 0x4000110C))  /* Request to Channel Map Register for SSP3 transmit Request */
#define DRCMR68		(*((volatile unsigned long *) 0x40001110))  /* Request to Channel Map Register for Camera FIFO 0 Request */
#define DRCMR69		(*((volatile unsigned long *) 0x40001114))  /* Request to Channel Map Register for Camera FIFO 1 Request */
#define DRCMR70		(*((volatile unsigned long *) 0x40001118))  /* Request to Channel Map Register for Camera FIFO 2 Request */
#define DRCMR71		(*((volatile unsigned long *) 0x4000111C))  /* Request to Channel Map Register for TPM receive Request */
#define DRCMR72		(*((volatile unsigned long *) 0x40001120))  /* Request to Channel Map Register for TPM transmit Request1 */
#define DRCMR73		(*((volatile unsigned long *) 0x40001124))  /* Request to Channel Map Register for TPM transmit Request2 */
#define DRCMR74		(*((volatile unsigned long *) 0x40001128))  /* Request to Channel Map Register for DREQ<2> */

#define DRCMR(n)	(*((volatile unsigned long *) (0x40000100 + ((n) << 2)) )) 

#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
#define DRCMR_CHLNUM	0x1f		/* mask for Channel Number (read / write) */

#define DDADR0		(*((volatile unsigned long *) 0x40000200))  /* DMA Descriptor Address Register Channel 0 */
#define DSADR0		(*((volatile unsigned long *) 0x40000204))  /* DMA Source Address Register Channel 0 */
#define DTADR0		(*((volatile unsigned long *) 0x40000208))  /* DMA Target Address Register Channel 0 */
#define DCMD0		(*((volatile unsigned long *) 0x4000020c))  /* DMA Command Address Register Channel 0 */
#define DDADR1		(*((volatile unsigned long *) 0x40000210))  /* DMA Descriptor Address Register Channel 1 */
#define DSADR1		(*((volatile unsigned long *) 0x40000214))  /* DMA Source Address Register Channel 1 */
#define DTADR1		(*((volatile unsigned long *) 0x40000218))  /* DMA Target Address Register Channel 1 */
#define DCMD1		(*((volatile unsigned long *) 0x4000021c))  /* DMA Command Address Register Channel 1 */
#define DDADR2		(*((volatile unsigned long *) 0x40000220))  /* DMA Descriptor Address Register Channel 2 */
#define DSADR2		(*((volatile unsigned long *) 0x40000224))  /* DMA Source Address Register Channel 2 */
#define DTADR2		(*((volatile unsigned long *) 0x40000228))  /* DMA Target Address Register Channel 2 */
#define DCMD2		(*((volatile unsigned long *) 0x4000022c))  /* DMA Command Address Register Channel 2 */
#define DDADR3		(*((volatile unsigned long *) 0x40000230))  /* DMA Descriptor Address Register Channel 3 */
#define DSADR3		(*((volatile unsigned long *) 0x40000234))  /* DMA Source Address Register Channel 3 */
#define DTADR3		(*((volatile unsigned long *) 0x40000238))  /* DMA Target Address Register Channel 3 */
#define DCMD3		(*((volatile unsigned long *) 0x4000023c))  /* DMA Command Address Register Channel 3 */
#define DDADR4		(*((volatile unsigned long *) 0x40000240))  /* DMA Descriptor Address Register Channel 4 */
#define DSADR4		(*((volatile unsigned long *) 0x40000244))  /* DMA Source Address Register Channel 4 */
#define DTADR4		(*((volatile unsigned long *) 0x40000248))  /* DMA Target Address Register Channel 4 */
#define DCMD4		(*((volatile unsigned long *) 0x4000024c))  /* DMA Command Address Register Channel 4 */
#define DDADR5		(*((volatile unsigned long *) 0x40000250))  /* DMA Descriptor Address Register Channel 5 */
#define DSADR5		(*((volatile unsigned long *) 0x40000254))  /* DMA Source Address Register Channel 5 */
#define DTADR5		(*((volatile unsigned long *) 0x40000258))  /* DMA Target Address Register Channel 5 */
#define DCMD5		(*((volatile unsigned long *) 0x4000025c))  /* DMA Command Address Register Channel 5 */
#define DDADR6		(*((volatile unsigned long *) 0x40000260))  /* DMA Descriptor Address Register Channel 6 */
#define DSADR6		(*((volatile unsigned long *) 0x40000264))  /* DMA Source Address Register Channel 6 */
#define DTADR6		(*((volatile unsigned long *) 0x40000268))  /* DMA Target Address Register Channel 6 */
#define DCMD6		(*((volatile unsigned long *) 0x4000026c))  /* DMA Command Address Register Channel 6 */
#define DDADR7		(*((volatile unsigned long *) 0x40000270))  /* DMA Descriptor Address Register Channel 7 */
#define DSADR7		(*((volatile unsigned long *) 0x40000274))  /* DMA Source Address Register Channel 7 */
#define DTADR7		(*((volatile unsigned long *) 0x40000278))  /* DMA Target Address Register Channel 7 */
#define DCMD7		(*((volatile unsigned long *) 0x4000027c))  /* DMA Command Address Register Channel 7 */
#define DDADR8		(*((volatile unsigned long *) 0x40000280))  /* DMA Descriptor Address Register Channel 8 */
#define DSADR8		(*((volatile unsigned long *) 0x40000284))  /* DMA Source Address Register Channel 8 */
#define DTADR8		(*((volatile unsigned long *) 0x40000288))  /* DMA Target Address Register Channel 8 */
#define DCMD8		(*((volatile unsigned long *) 0x4000028c))  /* DMA Command Address Register Channel 8 */
#define DDADR9		(*((volatile unsigned long *) 0x40000290))  /* DMA Descriptor Address Register Channel 9 */
#define DSADR9		(*((volatile unsigned long *) 0x40000294))  /* DMA Source Address Register Channel 9 */
#define DTADR9		(*((volatile unsigned long *) 0x40000298))  /* DMA Target Address Register Channel 9 */
#define DCMD9		(*((volatile unsigned long *) 0x4000029c))  /* DMA Command Address Register Channel 9 */
#define DDADR10		(*((volatile unsigned long *) 0x400002a0))  /* DMA Descriptor Address Register Channel 10 */
#define DSADR10		(*((volatile unsigned long *) 0x400002a4))  /* DMA Source Address Register Channel 10 */
#define DTADR10		(*((volatile unsigned long *) 0x400002a8))  /* DMA Target Address Register Channel 10 */
#define DCMD10		(*((volatile unsigned long *) 0x400002ac))  /* DMA Command Address Register Channel 10 */
#define DDADR11		(*((volatile unsigned long *) 0x400002b0))  /* DMA Descriptor Address Register Channel 11 */
#define DSADR11		(*((volatile unsigned long *) 0x400002b4))  /* DMA Source Address Register Channel 11 */
#define DTADR11		(*((volatile unsigned long *) 0x400002b8))  /* DMA Target Address Register Channel 11 */
#define DCMD11		(*((volatile unsigned long *) 0x400002bc))  /* DMA Command Address Register Channel 11 */
#define DDADR12		(*((volatile unsigned long *) 0x400002c0))  /* DMA Descriptor Address Register Channel 12 */
#define DSADR12		(*((volatile unsigned long *) 0x400002c4))  /* DMA Source Address Register Channel 12 */
#define DTADR12		(*((volatile unsigned long *) 0x400002c8))  /* DMA Target Address Register Channel 12 */
#define DCMD12		(*((volatile unsigned long *) 0x400002cc))  /* DMA Command Address Register Channel 12 */
#define DDADR13		(*((volatile unsigned long *) 0x400002d0))  /* DMA Descriptor Address Register Channel 13 */
#define DSADR13		(*((volatile unsigned long *) 0x400002d4))  /* DMA Source Address Register Channel 13 */
#define DTADR13		(*((volatile unsigned long *) 0x400002d8))  /* DMA Target Address Register Channel 13 */
#define DCMD13		(*((volatile unsigned long *) 0x400002dc))  /* DMA Command Address Register Channel 13 */
#define DDADR14		(*((volatile unsigned long *) 0x400002e0))  /* DMA Descriptor Address Register Channel 14 */
#define DSADR14		(*((volatile unsigned long *) 0x400002e4))  /* DMA Source Address Register Channel 14 */
#define DTADR14		(*((volatile unsigned long *) 0x400002e8))  /* DMA Target Address Register Channel 14 */
#define DCMD14		(*((volatile unsigned long *) 0x400002ec))  /* DMA Command Address Register Channel 14 */
#define DDADR15		(*((volatile unsigned long *) 0x400002f0))  /* DMA Descriptor Address Register Channel 15 */
#define DSADR15		(*((volatile unsigned long *) 0x400002f4))  /* DMA Source Address Register Channel 15 */
#define DTADR15		(*((volatile unsigned long *) 0x400002f8))  /* DMA Target Address Register Channel 15 */
#define DCMD15		(*((volatile unsigned long *) 0x400002fc))  /* DMA Command Address Register Channel 15 */

#define DDADR(x)	(*((volatile unsigned long *) (0x40000200 + ((x) << 4)) ))
#define DSADR(x)	(*((volatile unsigned long *) (0x40000204 + ((x) << 4)) )) 
#define DTADR(x)	(*((volatile unsigned long *) (0x40000208 + ((x) << 4)) )) 
#define DCMD(x)		(*((volatile unsigned long *) (0x4000020c + ((x) << 4)) )) 


#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
#define DDADR_STOP		(1 << 0)	/* Stop (read / write) */

#define DCMD_INCSRCADDR	(1 << 31)	/* Source Address Increment Setting. */
#define DCMD_INCTRGADDR	(1 << 30)	/* Target Address Increment Setting. */
#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
#define DCMD_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
#define DCMD_ENDIAN		(1 << 18)	/* Device Endian-ness. */
#define DCMD_BURST8		(1 << 16)	/* 8 byte burst */
#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
#define DCMD_WIDTH1		(1 << 14)	/* 1 byte width */
#define DCMD_WIDTH2		(2 << 14)	/* 2 byte width (HalfWord) */
#define DCMD_WIDTH4		(3 << 14)	/* 4 byte width (Word) */
#define DCMD_LENGTH		0x01fff		/* length mask (max = 8K - 1) */

/* default combinations */
#define DCMD_RXPCDR		(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_RXMCDR		(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR		(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)


/*
* UARTs
*/

/* Full Function UART (FFUART) */
#define FFUART		FFRBR
#define FFRBR		(*((volatile unsigned char *) 0x40100000))  /* Receive Buffer Register (read only) */
#define FFTHR		(*((volatile unsigned char *) 0x40100000))  /* Transmit Holding Register (write only) */
#define FFIER		(*((volatile unsigned char *) 0x40100004))  /* Interrupt Enable Register (read/write) */
#define FFIIR		(*((volatile unsigned char *) 0x40100008))  /* Interrupt ID Register (read only) */
#define FFFCR		(*((volatile unsigned char *) 0x40100008))  /* FIFO Control Register (write only) */
#define FFLCR		(*((volatile unsigned char *) 0x4010000C))  /* Line Control Register (read/write) */
#define FFMCR		(*((volatile unsigned char *) 0x40100010))  /* Modem Control Register (read/write) */
#define FFLSR		(*((volatile unsigned char *) 0x40100014))  /* Line Status Register (read only) */
#define FFMSR		(*((volatile unsigned char *) 0x40100018))  /* Modem Status Register (read only) */
#define FFSPR		(*((volatile unsigned char *) 0x4010001C))  /* Scratch Pad Register (read/write) */
#define FFISR		(*((volatile unsigned char *) 0x40100020))  /* Infrared Selection Register (read/write) */
#define FFDLL		(*((volatile unsigned char *) 0x40100000))  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define FFDLH		(*((volatile unsigned char *) 0x40100004))  /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define FFFOR    	(*((volatile unsigned char *) 0x40100024))	/* Receive FIFO Occupancy Register */
#define FFABR    	(*((volatile unsigned char *) 0x40100028))	/* Auto-Baud control Register */
#define FFACR    	(*((volatile unsigned char *) 0x4010002C))	/* Auto-baud Count Register */

/* Bluetooth UART (BTUART) */
#define BTUART		BTRBR
#define BTRBR		(*((volatile unsigned long *) 0x40200000))  /* Receive Buffer Register (read only) */
#define BTTHR		(*((volatile unsigned long *) 0x40200000))  /* Transmit Holding Register (write only) */
#define BTIER		(*((volatile unsigned long *) 0x40200004))  /* Interrupt Enable Register (read/write) */
#define BTIIR		(*((volatile unsigned long *) 0x40200008))  /* Interrupt ID Register (read only) */
#define BTFCR		(*((volatile unsigned long *) 0x40200008))  /* FIFO Control Register (write only) */
#define BTLCR		(*((volatile unsigned long *) 0x4020000C))  /* Line Control Register (read/write) */
#define BTMCR		(*((volatile unsigned long *) 0x40200010))  /* Modem Control Register (read/write) */
#define BTLSR		(*((volatile unsigned long *) 0x40200014))  /* Line Status Register (read only) */
#define BTMSR		(*((volatile unsigned long *) 0x40200018))  /* Modem Status Register (read only) */
#define BTSPR		(*((volatile unsigned long *) 0x4020001C))  /* Scratch Pad Register (read/write) */
#define BTISR		(*((volatile unsigned long *) 0x40200020))  /* Infrared Selection Register (read/write) */
#define BTDLL		(*((volatile unsigned long *) 0x40200000))  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define BTDLH		(*((volatile unsigned long *) 0x40200004))  /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define BTFOR    	(*((volatile unsigned char *) 0x40200024))	/* Receive FIFO Occupancy Register */
#define BTABR    	(*((volatile unsigned char *) 0x40200028))	/* Auto-Baud control Register */
#define BTACR    	(*((volatile unsigned char *) 0x4020002C))	/* Auto-baud Count Register */

/* Standard UART (STUART) */
#define STUART		STRBR
#define STRBR		(*((volatile unsigned long *) 0x40700000))  /* Receive Buffer Register (read only) */
#define STTHR		(*((volatile unsigned long *) 0x40700000))  /* Transmit Holding Register (write only) */
#define STIER		(*((volatile unsigned long *) 0x40700004))  /* Interrupt Enable Register (read/write) */
#define STIIR		(*((volatile unsigned long *) 0x40700008))  /* Interrupt ID Register (read only) */
#define STFCR		(*((volatile unsigned long *) 0x40700008))  /* FIFO Control Register (write only) */
#define STLCR		(*((volatile unsigned long *) 0x4070000C))  /* Line Control Register (read/write) */
#define STMCR		(*((volatile unsigned long *) 0x40700010))  /* Modem Control Register (read/write) */
#define STLSR		(*((volatile unsigned long *) 0x40700014))  /* Line Status Register (read only) */