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📄 pxa27x.h

📁 周立功PXA270教学实验箱的ARM汇编指令实验2
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/****************************************Copyright (c)**************************************************
**                              
**                                     
**                                 
**
**--------------File Info-------------------------------------------------------------------------------
** File Name: PXA27X.h
** Last modified Date: 2006-8-10
** Last Version: v1.0
** Description: PXA27X头文件
**
**------------------------------------------------------------------------------------------------------
** Created By: 黄绍斌
** Created date: 2006-8-10
** Version: v1.0
** Descriptions:
**
**------------------------------------------------------------------------------------------------------
** Modified by:
** Modified date: 
** Version:
** Descriptions:
**
********************************************************************************************************/
#ifndef __PXA27X_H
#define __PXA27X_H

/*
* PXA Chip selects
*/
#define PXA_CS0_PHYS       	0x00000000
#define PXA_CS1_PHYS	   	0x04000000
#define PXA_CS2_PHYS	   	0x08000000
#define PXA_CS3_PHYS	   	0x0C000000
#define PXA_CS4_PHYS	   	0x10000000
#define PXA_CS5_PHYS	   	0x14000000

/*
* PXA SDRAM banks
*/
#define PXA_SDRAM_BANK0	   	0xa0000000
#define PXA_SDRAM_BANK1	   	0xa4000000
#define PXA_SDRAM_BANK2		0xa8000000
#define PXA_SDRAM_BANK3		0xac000000


/*
* Personal Computer Memory Card International Association (PCMCIA) sockets
*/
#define PCMCIAPrtSp	   		0x04000000		/* PCMCIA Partition Space [byte]   */
#define PCMCIASp	   		(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
#define PCMCIAIOSp	   		PCMCIAPrtSp		/* PCMCIA I/O Space [byte]         */
#define PCMCIAAttrSp		PCMCIAPrtSp		/* PCMCIA Attribute Space [byte]   */
#define PCMCIAMemSp			PCMCIAPrtSp		/* PCMCIA Memory Space [byte]      */

#define PCMCIA0Sp			PCMCIASp		/* PCMCIA 0 Space [byte]           */
#define PCMCIA0IOSp			PCMCIAIOSp		/* PCMCIA 0 I/O Space [byte]       */
#define PCMCIA0AttrSp		PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp		PCMCIAMemSp		/* PCMCIA 0 Memory Space [byte]    */

#define PCMCIA1Sp			PCMCIASp		/* PCMCIA 1 Space [byte]           */
#define PCMCIA1IOSp			PCMCIAIOSp		/* PCMCIA 1 I/O Space [byte]       */
#define PCMCIA1AttrSp		PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp		PCMCIAMemSp		/* PCMCIA 1 Memory Space [byte]    */

#define _PCMCIA(Nb)	       	(0x20000000 + (Nb)*PCMCIASp)	/* PCMCIA [0..1]                   */                	
#define _PCMCIAIO(Nb)		_PCMCIA(Nb)						/* PCMCIA I/O [0..1]               */
#define _PCMCIAAttr(Nb)	    (_PCMCIA(Nb) + 2*PCMCIAPrtSp)  	/* PCMCIA Attribute [0..1]         */                 	
#define _PCMCIAMem(Nb)		(_PCMCIA(Nb) + 3*PCMCIAPrtSp)  	/* PCMCIA Memory [0..1]            */                 	
#define _PCMCIA0			_PCMCIA(0)		/* PCMCIA 0                        */
#define _PCMCIA0IO			_PCMCIAIO(0)	/* PCMCIA 0 I/O                    */
#define _PCMCIA0Attr		_PCMCIAAttr(0)	/* PCMCIA 0 Attribute              */
#define _PCMCIA0Mem			_PCMCIAMem(0)	/* PCMCIA 0 Memory                 */

#define _PCMCIA1			_PCMCIA(1)		/* PCMCIA 1                        */
#define _PCMCIA1IO			_PCMCIAIO(1)	/* PCMCIA 1 I/O                    */
#define _PCMCIA1Attr		_PCMCIAAttr(1)	/* PCMCIA 1 Attribute              */
#define _PCMCIA1Mem			_PCMCIAMem(1)	/* PCMCIA 1 Memory                 */



/*
* DMA Controller
*/
#define DCSR0		(*((volatile unsigned long *) 0x40000000)) 	/* DMA Control / Status Register for Channel 0 */
#define DCSR1		(*((volatile unsigned long *) 0x40000004))  /* DMA Control / Status Register for Channel 1 */
#define DCSR2		(*((volatile unsigned long *) 0x40000008))  /* DMA Control / Status Register for Channel 2 */
#define DCSR3		(*((volatile unsigned long *) 0x4000000c))  /* DMA Control / Status Register for Channel 3 */
#define DCSR4		(*((volatile unsigned long *) 0x40000010))  /* DMA Control / Status Register for Channel 4 */
#define DCSR5		(*((volatile unsigned long *) 0x40000014))  /* DMA Control / Status Register for Channel 5 */
#define DCSR6		(*((volatile unsigned long *) 0x40000018))  /* DMA Control / Status Register for Channel 6 */
#define DCSR7		(*((volatile unsigned long *) 0x4000001c))  /* DMA Control / Status Register for Channel 7 */
#define DCSR8		(*((volatile unsigned long *) 0x40000020))  /* DMA Control / Status Register for Channel 8 */
#define DCSR9		(*((volatile unsigned long *) 0x40000024))  /* DMA Control / Status Register for Channel 9 */
#define DCSR10		(*((volatile unsigned long *) 0x40000028))  /* DMA Control / Status Register for Channel 10 */
#define DCSR11		(*((volatile unsigned long *) 0x4000002c))  /* DMA Control / Status Register for Channel 11 */
#define DCSR12		(*((volatile unsigned long *) 0x40000030))  /* DMA Control / Status Register for Channel 12 */
#define DCSR13		(*((volatile unsigned long *) 0x40000034))  /* DMA Control / Status Register for Channel 13 */
#define DCSR14		(*((volatile unsigned long *) 0x40000038))  /* DMA Control / Status Register for Channel 14 */
#define DCSR15		(*((volatile unsigned long *) 0x4000003c))  /* DMA Control / Status Register for Channel 15 */
#define DCSR16		(*((volatile unsigned long *) 0x40000040)) 	/* DMA Control / Status Register for Channel 16 */
#define DCSR17		(*((volatile unsigned long *) 0x40000044))  /* DMA Control / Status Register for Channel 17 */
#define DCSR18		(*((volatile unsigned long *) 0x40000048))  /* DMA Control / Status Register for Channel 18 */
#define DCSR19		(*((volatile unsigned long *) 0x4000004c))  /* DMA Control / Status Register for Channel 19 */
#define DCSR20		(*((volatile unsigned long *) 0x40000050))  /* DMA Control / Status Register for Channel 20 */
#define DCSR21		(*((volatile unsigned long *) 0x40000054))  /* DMA Control / Status Register for Channel 21 */
#define DCSR22		(*((volatile unsigned long *) 0x40000058))  /* DMA Control / Status Register for Channel 22 */
#define DCSR23		(*((volatile unsigned long *) 0x4000005c))  /* DMA Control / Status Register for Channel 23 */
#define DCSR24		(*((volatile unsigned long *) 0x40000060))  /* DMA Control / Status Register for Channel 24 */
#define DCSR25		(*((volatile unsigned long *) 0x40000064))  /* DMA Control / Status Register for Channel 25 */
#define DCSR26		(*((volatile unsigned long *) 0x40000068))  /* DMA Control / Status Register for Channel 26 */
#define DCSR27		(*((volatile unsigned long *) 0x4000006c))  /* DMA Control / Status Register for Channel 27 */
#define DCSR28		(*((volatile unsigned long *) 0x40000070))  /* DMA Control / Status Register for Channel 28 */
#define DCSR29		(*((volatile unsigned long *) 0x40000074))  /* DMA Control / Status Register for Channel 29 */
#define DCSR30		(*((volatile unsigned long *) 0x40000078))  /* DMA Control / Status Register for Channel 30 */
#define DCSR31		(*((volatile unsigned long *) 0x4000007c))  /* DMA Control / Status Register for Channel 31 */

#define DCSR(x)		(*((volatile unsigned long *) (0x40000000 + ((x) << 2)) ))


#define DCSR_RUN		(1 << 31)	/* Run Bit (read / write) */
#define DCSR_NODESC		(1 << 30)	/* No-Descriptor Fetch (read / write) */
#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */

#define DCSR_EORIRQEN	(1 << 28)  	/* End of Receive Interrupt Enable (R/W) */
#define DCSR_EORJMPEN	(1 << 27)   /* Jump to next descriptor on EOR */
#define DCSR_EORSTOPEN	(1 << 26)   /* STOP on an EOR */
#define DCSR_SETCMPST	(1 << 25)   /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST	(1 << 24)   /* Clear Descriptor Compare Status */
#define DCSR_CMPST		(1 << 10)   /* The Descriptor Compare Status */
#define DCSR_ENRINTR	(1 << 9)  	/* The end of Receive */

#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
#define DCSR_BUSERR		(1 << 0)	/* Bus Error Interrupt (read / write) */

#define DINT		(*((volatile unsigned long *) 0x400000f0))  /* DMA Interrupt Register */
#define DRCMR0		(*((volatile unsigned long *) 0x40000100))  /* Request to Channel Map Register for DREQ 0 */
#define DRCMR1		(*((volatile unsigned long *) 0x40000104))  /* Request to Channel Map Register for DREQ 1 */
#define DRCMR2		(*((volatile unsigned long *) 0x40000108))  /* Request to Channel Map Register for I2S receive Request */
#define DRCMR3		(*((volatile unsigned long *) 0x4000010c))  /* Request to Channel Map Register for I2S transmit Request */
#define DRCMR4		(*((volatile unsigned long *) 0x40000110))  /* Request to Channel Map Register for BTUART receive Request */
#define DRCMR5		(*((volatile unsigned long *) 0x40000114))  /* Request to Channel Map Register for BTUART transmit Request. */
#define DRCMR6		(*((volatile unsigned long *) 0x40000118))  /* Request to Channel Map Register for FFUART receive Request */
#define DRCMR7		(*((volatile unsigned long *) 0x4000011c))  /* Request to Channel Map Register for FFUART transmit Request */
#define DRCMR8		(*((volatile unsigned long *) 0x40000120))  /* Request to Channel Map Register for AC97 microphone Request */
#define DRCMR9		(*((volatile unsigned long *) 0x40000124))  /* Request to Channel Map Register for AC97 modem receive Request */
#define DRCMR10		(*((volatile unsigned long *) 0x40000128))  /* Request to Channel Map Register for AC97 modem transmit Request */
#define DRCMR11		(*((volatile unsigned long *) 0x4000012c))  /* Request to Channel Map Register for AC97 audio receive Request */
#define DRCMR12		(*((volatile unsigned long *) 0x40000130))  /* Request to Channel Map Register for AC97 audio transmit Request */
#define DRCMR13		(*((volatile unsigned long *) 0x40000134))  /* Request to Channel Map Register for SSP1 receive Request */
#define DRCMR14		(*((volatile unsigned long *) 0x40000138))  /* Request to Channel Map Register for SSP1 transmit Request */
#define DRCMR15		(*((volatile unsigned long *) 0x4000013c))  /* Request to Channel Map Register for SSP2 receive Request */
#define DRCMR16		(*((volatile unsigned long *) 0x40000140))  /* Request to Channel Map Register for SSP2 transmit Request */
#define DRCMR17		(*((volatile unsigned long *) 0x40000144))  /* Request to Channel Map Register for ICP receive Request */
#define DRCMR18		(*((volatile unsigned long *) 0x40000148))  /* Request to Channel Map Register for ICP transmit Request */
#define DRCMR19		(*((volatile unsigned long *) 0x4000014c))  /* Request to Channel Map Register for STUART receive Request */
#define DRCMR20		(*((volatile unsigned long *) 0x40000150))  /* Request to Channel Map Register for STUART transmit Request */
#define DRCMR21		(*((volatile unsigned long *) 0x40000154))  /* Request to Channel Map Register for MMC receive Request */
#define DRCMR22		(*((volatile unsigned long *) 0x40000158))  /* Request to Channel Map Register for MMC transmit Request */
#define DRCMR23		(*((volatile unsigned long *) 0x4000015c))  /* Reserved */
#define DRCMR24		(*((volatile unsigned long *) 0x40000160))  /* Request to Channel Map Register for USB endpoint 0 Request */
#define DRCMR25		(*((volatile unsigned long *) 0x40000164))  /* Request to Channel Map Register for USB endpoint A Request */
#define DRCMR26		(*((volatile unsigned long *) 0x40000168))  /* Request to Channel Map Register for USB endpoint B Request */
#define DRCMR27		(*((volatile unsigned long *) 0x4000016C))  /* Request to Channel Map Register for USB endpoint C Request */
#define DRCMR28		(*((volatile unsigned long *) 0x40000170))  /* Request to Channel Map Register for USB endpoint D Request */
#define DRCMR29		(*((volatile unsigned long *) 0x40000174))  /* Request to Channel Map Register for USB endpoint E Request */
#define DRCMR30		(*((volatile unsigned long *) 0x40000178))  /* Request to Channel Map Register for USB endpoint F Request */
#define DRCMR31		(*((volatile unsigned long *) 0x4000017C))  /* Request to Channel Map Register for USB endpoint G Request */
#define DRCMR32		(*((volatile unsigned long *) 0x40000180))  /* Request to Channel Map Register for USB endpoint H Request */
#define DRCMR33		(*((volatile unsigned long *) 0x40000184))  /* Request to Channel Map Register for USB endpoint I Request */
#define DRCMR34		(*((volatile unsigned long *) 0x40000188))  /* Request to Channel Map Register for USB endpoint J Request */
#define DRCMR35		(*((volatile unsigned long *) 0x4000018C))  /* Request to Channel Map Register for USB endpoint K Request */
#define DRCMR36		(*((volatile unsigned long *) 0x40000190))  /* Request to Channel Map Register for USB endpoint L Request */
#define DRCMR37		(*((volatile unsigned long *) 0x40000194))  /* Request to Channel Map Register for USB endpoint M Request */
#define DRCMR38		(*((volatile unsigned long *) 0x40000198))  /* Request to Channel Map Register for USB endpoint N Request */
#define DRCMR39		(*((volatile unsigned long *) 0x4000019C))  /* Request to Channel Map Register for USB endpoint P Request */
#define DRCMR40		(*((volatile unsigned long *) 0x400001A0))  /* Request to Channel Map Register for USB endpoint Q Request */
#define DRCMR41		(*((volatile unsigned long *) 0x400001A4))  /* Request to Channel Map Register for USB endpoint R Request */
#define DRCMR42		(*((volatile unsigned long *) 0x400001A8))  /* Request to Channel Map Register for USB endpoint S Request */
#define DRCMR43		(*((volatile unsigned long *) 0x400001AC))  /* Request to Channel Map Register for USB endpoint T Request */
#define DRCMR44		(*((volatile unsigned long *) 0x400001B0))  /* Request to Channel Map Register for USB endpoint U Request */

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