⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 flashrw.lst

📁 aduc7026裸机程序
💻 LST
字号:
ARM COMPILER V2.42,  FlashRW                                                               17/01/09  22:24:15  PAGE 1   


ARM COMPILER V2.42, COMPILATION OF MODULE FlashRW
OBJECT MODULE PLACED IN FlashRW.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe FlashRW.c THUMB BROWSE DEBUG TABS(4) 

stmt  level    source

    1          #include "main.H"
    2           
    3          unsigned int FlashReadByte(unsigned long addr)
    4          {
    5   1          unsigned long tmpSta = 0;
    6   1          unsigned int  tmpVal = 0;
    7   1      
    8   1          FEEPRO = 0xEFFFFEFF;    
    9   1          FEEADR = addr;
   10   1          FEECON = 0x01;
   11   1          tmpVal = FEEDAT;
   12   1          tmpSta = FEESTA;
   13   1          while((tmpSta & 0x04)){
   14   2              tmpSta = FEESTA;
   15   2          } 
   16   1          FEEMOD &= 0x7F;    //disable read
   17   1          if((tmpSta & 0x02)){
   18   2              return (1);
   19   2          }else{
   20   2              return tmpVal;
   21   2          } 
   22   1      }
   23          unsigned int FlashWriteByte(unsigned long addr,unsigned int halfword)
   24          {
   25   1          unsigned long tmpSta = 0;
   26   1          FEEPRO = 0xFFFFFEFF;
   27   1          FEEMOD = 0x048;     //enable erase/write
   28   1          FEEADR = 0x1234;
   29   1          FEEDAT = 0x5678;
   30   1          FEECON = 0x0c;
   31   1          FEEADR = addr;
   32   1          FEEDAT = halfword;
   33   1          FEECON = 0x03;      //first erase then write
   34   1      
   35   1          tmpSta = FEESTA;
   36   1          while((tmpSta & 0x04)){
   37   2              tmpSta = FEESTA;
   38   2          }
   39   1          FEEPRO = 0xFFFFFFFF;
   40   1          FEEMOD = 0x00;      //disable erase/write 
   41   1          if((tmpSta & 0x02)){
   42   2              return (1);
   43   2          }else{
   44   2              return (0);
   45   2          }
   46   1      }
ARM COMPILER V2.42,  FlashRW                                                               17/01/09  22:24:15  PAGE 2   

ASSEMBLY LISTING OF GENERATED OBJECT CODE



*** PUBLICS:
 PUBLIC         FlashReadByte?T
 PUBLIC         FlashWriteByte?T



*** CODE SEGMENT '?PR?FlashReadByte?T?FlashRW':
    3: unsigned int FlashReadByte(unsigned long addr)
 00000000  B410      PUSH        {R4}
 00000002  1C02      MOV         R2,R0 ; addr
 00000004  ---- Variable 'addr' assigned to Register 'R2' ----
    4: {
 00000004            ; SCOPE-START
    5:     unsigned long tmpSta = 0;
 00000004  2300      MOV         R3,#0x0
 00000006  ---- Variable 'tmpSta' assigned to Register 'R3' ----
    6:     unsigned int  tmpVal = 0;
 00000006  2100      MOV         R1,#0x0
 00000008  ---- Variable 'tmpVal' assigned to Register 'R1' ----
    8:     FEEPRO = 0xEFFFFEFF;    
 00000008  4800      LDR         R1,=0xEFFFFEFF
 0000000A  4800      LDR         R0,=0xFFFFF81C
 0000000C  6001      STR         R1,[R0,#0x0]
    9:     FEEADR = addr;
 0000000E  1C11      MOV         R1,R2 ; addr
 00000010  4800      LDR         R0,=0xFFFFF810
 00000012  6001      STR         R1,[R0,#0x0]
   10:     FEECON = 0x01;
 00000014  2101      MOV         R1,#0x1
 00000016  4800      LDR         R0,=0xFFFFF808
 00000018  6001      STR         R1,[R0,#0x0]
   11:     tmpVal = FEEDAT;
 0000001A  4800      LDR         R0,=0xFFFFF80C
 0000001C  6801      LDR         R1,[R0,#0x0]
   12:     tmpSta = FEESTA;
 0000001E  4800      LDR         R0,=0xFFFFF800
 00000020  6803      LDR         R3,[R0,#0x0]
   13:     while((tmpSta & 0x04)){
 00000022  E001      B           L_1  ; T=0x00000028
 00000024          L_3:
   14:         tmpSta = FEESTA;
 00000024  4800      LDR         R0,=0xFFFFF800
 00000026  6803      LDR         R3,[R0,#0x0]
   15:     } 
 00000028          L_1:
 00000028  1C18      MOV         R0,R3 ; tmpSta
 0000002A  2204      MOV         R2,#0x4
 0000002C  4210      TST         R0,R2 ; tmpSta
 0000002E  D1F9      BNE         L_3  ; T=0x00000024
   16:     FEEMOD &= 0x7F;    //disable read
 00000030  247F      MOV         R4,#0x7F
 00000032  4800      LDR         R0,=0xFFFFF804
 00000034  6802      LDR         R2,[R0,#0x0]
 00000036  4022      AND         R2,R4
 00000038  6002      STR         R2,[R0,#0x0]
   17:     if((tmpSta & 0x02)){
 0000003A  1C18      MOV         R0,R3 ; tmpSta
 0000003C  2202      MOV         R2,#0x2
 0000003E  4210      TST         R0,R2 ; tmpSta
 00000040  D001      BEQ         L_5  ; T=0x00000046
   18:         return (1);
 00000042  2001      MOV         R0,#0x1
 00000044  E000      B           L_6  ; T=0x00000048
   19:     }else{
 00000046          L_5:
ARM COMPILER V2.42,  FlashRW                                                               17/01/09  22:24:15  PAGE 3   

   20:         return tmpVal;
 00000046  1C08      MOV         R0,R1 ; tmpVal
   21:     } 
 00000048            ; SCOPE-END
   22: }
 00000048          L_6:
 00000048  BC10      POP         {R4}
 0000004A  4770      BX          R14
 0000004C          ENDP ; 'FlashReadByte?T'


*** CODE SEGMENT '?PR?FlashWriteByte?T?FlashRW':
   23: unsigned int FlashWriteByte(unsigned long addr,unsigned int halfword)
 00000000  B430      PUSH        {R4-R5}
 00000002  1C0C      MOV         R4,R1 ; halfword
 00000004  ---- Variable 'halfword' assigned to Register 'R4' ----
 00000004  1C05      MOV         R5,R0 ; addr
 00000006  ---- Variable 'addr' assigned to Register 'R5' ----
   24: {
 00000006            ; SCOPE-START
   25:     unsigned long tmpSta = 0;
 00000006  2300      MOV         R3,#0x0
 00000008  1C1A      MOV         R2,R3 ; tmpSta
 0000000A  ---- Variable 'tmpSta' assigned to Register 'R2' ----
   26:     FEEPRO = 0xFFFFFEFF;
 0000000A  4800      LDR         R1,=0xFFFFFEFF
 0000000C  4800      LDR         R0,=0xFFFFF81C
 0000000E  6001      STR         R1,[R0,#0x0]
   27:     FEEMOD = 0x048;     //enable erase/write
 00000010  2148      MOV         R1,#0x48
 00000012  4800      LDR         R0,=0xFFFFF804
 00000014  6001      STR         R1,[R0,#0x0]
   28:     FEEADR = 0x1234;
 00000016  4800      LDR         R1,=0x1234
 00000018  4800      LDR         R0,=0xFFFFF810
 0000001A  6001      STR         R1,[R0,#0x0]
   29:     FEEDAT = 0x5678;
 0000001C  4800      LDR         R1,=0x5678
 0000001E  4800      LDR         R0,=0xFFFFF80C
 00000020  6001      STR         R1,[R0,#0x0]
   30:     FEECON = 0x0c;
 00000022  210C      MOV         R1,#0xC
 00000024  4800      LDR         R0,=0xFFFFF808
 00000026  6001      STR         R1,[R0,#0x0]
   31:     FEEADR = addr;
 00000028  1C29      MOV         R1,R5 ; addr
 0000002A  4800      LDR         R0,=0xFFFFF810
 0000002C  6001      STR         R1,[R0,#0x0]
   32:     FEEDAT = halfword;
 0000002E  1C21      MOV         R1,R4 ; halfword
 00000030  4800      LDR         R0,=0xFFFFF80C
 00000032  6001      STR         R1,[R0,#0x0]
   33:     FEECON = 0x03;      //first erase then write
 00000034  2103      MOV         R1,#0x3
 00000036  4800      LDR         R0,=0xFFFFF808
 00000038  6001      STR         R1,[R0,#0x0]
   35:     tmpSta = FEESTA;
 0000003A  4800      LDR         R0,=0xFFFFF800
 0000003C  6802      LDR         R2,[R0,#0x0]
   36:     while((tmpSta & 0x04)){
 0000003E  E001      B           L_8  ; T=0x00000044
 00000040          L_10:
   37:         tmpSta = FEESTA;
 00000040  4800      LDR         R0,=0xFFFFF800
 00000042  6802      LDR         R2,[R0,#0x0]
   38:     }
 00000044          L_8:
 00000044  1C10      MOV         R0,R2 ; tmpSta
ARM COMPILER V2.42,  FlashRW                                                               17/01/09  22:24:15  PAGE 4   

 00000046  2104      MOV         R1,#0x4
 00000048  4208      TST         R0,R1 ; tmpSta
 0000004A  D1F9      BNE         L_10  ; T=0x00000040
   39:     FEEPRO = 0xFFFFFFFF;
 0000004C  4800      LDR         R1,=0xFFFFFFFF
 0000004E  4800      LDR         R0,=0xFFFFF81C
 00000050  6001      STR         R1,[R0,#0x0]
   40:     FEEMOD = 0x00;      //disable erase/write 
 00000052  4800      LDR         R0,=0xFFFFF804
 00000054  6003      STR         R3,[R0,#0x0]
   41:     if((tmpSta & 0x02)){
 00000056  1C10      MOV         R0,R2 ; tmpSta
 00000058  2102      MOV         R1,#0x2
 0000005A  4208      TST         R0,R1 ; tmpSta
 0000005C  D001      BEQ         L_12  ; T=0x00000062
   42:         return (1);
 0000005E  2001      MOV         R0,#0x1
 00000060  E000      B           L_13  ; T=0x00000064
   43:     }else{
 00000062          L_12:
   44:         return (0);
 00000062  2000      MOV         R0,#0x0
   45:     }
 00000064            ; SCOPE-END
 00000064          L_13:
 00000064  BC30      POP         {R4-R5}
 00000066  4770      BX          R14
 00000068          ENDP ; 'FlashWriteByte?T'



Module Information          Static
----------------------------------
  code size            =    ------
  data size            =    ------
  const size           =    ------
End of Module Information.


ARM COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -