prev_cmp_freq2_2.qmsg

奇数分频:2.2倍分频,其他任意奇数倍的分频可扩展得到.

{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "203 " "Info: Peak virtual memory: 203 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 21 15:14:01 2008 " "Info: Processing ended: Sun Dec 21 15:14:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Info: Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 21 15:14:05 2008 " "Info: Processing started: Sun Dec 21 15:14:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off freq2_2 -c freq2_2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off freq2_2 -c freq2_2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } } { "d:/eda/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/eda/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count\[0\] freq\[1\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"count\[0\]\" and destination register \"freq\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.045 ns + Longest register register " "Info: + Longest register to register delay is 2.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LCFF_X1_Y29_N27 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y29_N27; Fanout = 6; REG Node = 'count\[0\]'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[0] } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.150 ns) 1.099 ns Add1~93 2 COMB LCCOMB_X1_Y29_N30 2 " "Info: 2: + IC(0.949 ns) + CELL(0.150 ns) = 1.099 ns; Loc. = LCCOMB_X1_Y29_N30; Fanout = 2; COMB Node = 'Add1~93'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.099 ns" { count[0] Add1~93 } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.437 ns) 1.961 ns freq\[1\]~323 3 COMB LCCOMB_X1_Y29_N4 1 " "Info: 3: + IC(0.425 ns) + CELL(0.437 ns) = 1.961 ns; Loc. = LCCOMB_X1_Y29_N4; Fanout = 1; COMB Node = 'freq\[1\]~323'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.862 ns" { Add1~93 freq[1]~323 } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.045 ns freq\[1\] 4 REG LCFF_X1_Y29_N5 5 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.045 ns; Loc. = LCFF_X1_Y29_N5; Fanout = 5; REG Node = 'freq\[1\]'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { freq[1]~323 freq[1] } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.671 ns ( 32.81 % ) " "Info: Total cell delay = 0.671 ns ( 32.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.374 ns ( 67.19 % ) " "Info: Total interconnect delay = 1.374 ns ( 67.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.045 ns" { count[0] Add1~93 freq[1]~323 freq[1] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.045 ns" { count[0] {} Add1~93 {} freq[1]~323 {} freq[1] {} } { 0.000ns 0.949ns 0.425ns 0.000ns } { 0.000ns 0.150ns 0.437ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.654 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 7 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.654 ns freq\[1\] 3 REG LCFF_X1_Y29_N5 5 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X1_Y29_N5; Fanout = 5; REG Node = 'freq\[1\]'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { clk~clkctrl freq[1] } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.87 % ) " "Info: Total cell delay = 1.536 ns ( 57.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.118 ns ( 42.13 % ) " "Info: Total interconnect delay = 1.118 ns ( 42.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl freq[1] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} freq[1] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.654 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 7 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.654 ns count\[0\] 3 REG LCFF_X1_Y29_N27 6 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X1_Y29_N27; Fanout = 6; REG Node = 'count\[0\]'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { clk~clkctrl count[0] } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.87 % ) " "Info: Total cell delay = 1.536 ns ( 57.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.118 ns ( 42.13 % ) " "Info: Total interconnect delay = 1.118 ns ( 42.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} count[0] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl freq[1] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} freq[1] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} count[0] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.045 ns" { count[0] Add1~93 freq[1]~323 freq[1] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.045 ns" { count[0] {} Add1~93 {} freq[1]~323 {} freq[1] {} } { 0.000ns 0.949ns 0.425ns 0.000ns } { 0.000ns 0.150ns 0.437ns 0.084ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl freq[1] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} freq[1] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} count[0] {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { freq[1] } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { freq[1] {} } {  } {  } "" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk freq2_2 freq2_2~reg0 6.068 ns register " "Info: tco from clock \"clk\" to destination pin \"freq2_2\" through register \"freq2_2~reg0\" is 6.068 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.654 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 7 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.537 ns) 2.654 ns freq2_2~reg0 3 REG LCFF_X1_Y29_N9 2 " "Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X1_Y29_N9; Fanout = 2; REG Node = 'freq2_2~reg0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { clk~clkctrl freq2_2~reg0 } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.87 % ) " "Info: Total cell delay = 1.536 ns ( 57.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.118 ns ( 42.13 % ) " "Info: Total interconnect delay = 1.118 ns ( 42.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl freq2_2~reg0 } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} freq2_2~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.164 ns + Longest register pin " "Info: + Longest register to pin delay is 3.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freq2_2~reg0 1 REG LCFF_X1_Y29_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y29_N9; Fanout = 2; REG Node = 'freq2_2~reg0'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { freq2_2~reg0 } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 12 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(2.642 ns) 3.164 ns freq2_2 2 PIN PIN_G3 0 " "Info: 2: + IC(0.522 ns) + CELL(2.642 ns) = 3.164 ns; Loc. = PIN_G3; Fanout = 0; PIN Node = 'freq2_2'" {  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.164 ns" { freq2_2~reg0 freq2_2 } "NODE_NAME" } } { "freq2_2.v" "" { Text "D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 83.50 % ) " "Info: Total cell delay = 2.642 ns ( 83.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.522 ns ( 16.50 % ) " "Info: Total interconnect delay = 0.522 ns ( 16.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.164 ns" { freq2_2~reg0 freq2_2 } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "3.164 ns" { freq2_2~reg0 {} freq2_2 {} } { 0.000ns 0.522ns } { 0.000ns 2.642ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk clk~clkctrl freq2_2~reg0 } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk {} clk~combout {} clk~clkctrl {} freq2_2~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.000ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.164 ns" { freq2_2~reg0 freq2_2 } "NODE_NAME" } } { "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/eda/altera/80/quartus/bin/Technology_Viewer.qrui" "3.164 ns" { freq2_2~reg0 {} freq2_2 {} } { 0.000ns 0.522ns } { 0.000ns 2.642ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 21 15:14:07 2008 " "Info: Processing ended: Sun Dec 21 15:14:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 21 15:14:20 2008 " "Info: Processing started: Sun Dec 21 15:14:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off freq2_2 -c freq2_2 " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off freq2_2 -c freq2_2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "freq2_2.vo freq2_2_v.sdo D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/simulation/modelsim/ simulation " "Info: Generated files \"freq2_2.vo\" and \"freq2_2_v.sdo\" in directory \"D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Peak virtual memory: 118 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 21 15:14:23 2008 " "Info: Processing ended: Sun Dec 21 15:14:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 5 s " "Info: Quartus II Full Compilation was successful. 0 errors, 5 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}