📄 freq2_2.v.bak
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module freq2_2(//input
clk,
//output
freq2_2
);
input clk;
output reg freq2_2;
reg [2:0] count,freq;
always@(posedge clk)
begin
count<=count+3'd1;
if(freq<=3) //4 times
begin
if(count==1)
begin
count<=0; //freq/2
freq2_2<=1;
freq<=freq+3'd1;
end
else
freq2_2<=0;
end
else if(freq==4) //1 time
begin
if(count==3) //freq/3
begin
count<=0;
freq2_2<=1;
freq<=0;
end
else
freq2_2<=0;
end
end
endmodule
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