freq2_2.tan.rpt

奇数分频:2.2倍分频,其他任意奇数倍的分频可扩展得到.

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[0]      ; count[1]     ; clk        ; clk      ; None                        ; None                      ; 1.908 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[1]      ; count[0]     ; clk        ; clk      ; None                        ; None                      ; 1.782 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[1]      ; count[1]     ; clk        ; clk      ; None                        ; None                      ; 1.781 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[0]      ; freq[1]      ; clk        ; clk      ; None                        ; None                      ; 1.731 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[0]      ; freq[2]      ; clk        ; clk      ; None                        ; None                      ; 1.730 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; count[0]     ; clk        ; clk      ; None                        ; None                      ; 1.724 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; count[1]     ; clk        ; clk      ; None                        ; None                      ; 1.723 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; freq[1]      ; clk        ; clk      ; None                        ; None                      ; 1.688 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; freq[2]      ; clk        ; clk      ; None                        ; None                      ; 1.687 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; freq2_2~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.666 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[2]      ; count[0]     ; clk        ; clk      ; None                        ; None                      ; 1.664 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; freq[0]      ; clk        ; clk      ; None                        ; None                      ; 1.664 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[2]      ; count[1]     ; clk        ; clk      ; None                        ; None                      ; 1.663 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; freq[1]      ; clk        ; clk      ; None                        ; None                      ; 1.643 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; freq[2]      ; clk        ; clk      ; None                        ; None                      ; 1.642 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[1]      ; freq2_2~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.579 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; count[0]     ; clk        ; clk      ; None                        ; None                      ; 1.494 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; count[1]     ; clk        ; clk      ; None                        ; None                      ; 1.493 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[1]      ; freq[1]      ; clk        ; clk      ; None                        ; None                      ; 1.482 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[1]      ; freq[0]      ; clk        ; clk      ; None                        ; None                      ; 1.481 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[1]      ; freq[2]      ; clk        ; clk      ; None                        ; None                      ; 1.475 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; freq2_2~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.436 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; freq[0]      ; clk        ; clk      ; None                        ; None                      ; 1.434 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[0]      ; freq2_2~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.401 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq2_2~reg0 ; freq2_2~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.363 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[2]      ; freq[1]      ; clk        ; clk      ; None                        ; None                      ; 1.277 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[2]      ; freq2_2~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[2]      ; freq[0]      ; clk        ; clk      ; None                        ; None                      ; 1.276 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[0]      ; freq[0]      ; clk        ; clk      ; None                        ; None                      ; 1.272 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; freq[2]      ; freq[2]      ; clk        ; clk      ; None                        ; None                      ; 1.270 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[0]     ; count[2]     ; clk        ; clk      ; None                        ; None                      ; 1.184 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[1]     ; count[2]     ; clk        ; clk      ; None                        ; None                      ; 0.865 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; count[2]     ; count[2]     ; clk        ; clk      ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.068 ns   ; freq2_2~reg0 ; freq2_2 ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sun Dec 21 15:14:05 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off freq2_2 -c freq2_2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "count[0]" and destination register "freq[1]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.045 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y29_N27; Fanout = 6; REG Node = 'count[0]'
            Info: 2: + IC(0.949 ns) + CELL(0.150 ns) = 1.099 ns; Loc. = LCCOMB_X1_Y29_N30; Fanout = 2; COMB Node = 'Add1~93'
            Info: 3: + IC(0.425 ns) + CELL(0.437 ns) = 1.961 ns; Loc. = LCCOMB_X1_Y29_N4; Fanout = 1; COMB Node = 'freq[1]~323'
            Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.045 ns; Loc. = LCFF_X1_Y29_N5; Fanout = 5; REG Node = 'freq[1]'
            Info: Total cell delay = 0.671 ns ( 32.81 % )
            Info: Total interconnect delay = 1.374 ns ( 67.19 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.654 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X1_Y29_N5; Fanout = 5; REG Node = 'freq[1]'
                Info: Total cell delay = 1.536 ns ( 57.87 % )
                Info: Total interconnect delay = 1.118 ns ( 42.13 % )
            Info: - Longest clock path from clock "clk" to source register is 2.654 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X1_Y29_N27; Fanout = 6; REG Node = 'count[0]'
                Info: Total cell delay = 1.536 ns ( 57.87 % )
                Info: Total interconnect delay = 1.118 ns ( 42.13 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk" to destination pin "freq2_2" through register "freq2_2~reg0" is 6.068 ns
    Info: + Longest clock path from clock "clk" to source register is 2.654 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.000 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X1_Y29_N9; Fanout = 2; REG Node = 'freq2_2~reg0'
        Info: Total cell delay = 1.536 ns ( 57.87 % )
        Info: Total interconnect delay = 1.118 ns ( 42.13 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.164 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y29_N9; Fanout = 2; REG Node = 'freq2_2~reg0'
        Info: 2: + IC(0.522 ns) + CELL(2.642 ns) = 3.164 ns; Loc. = PIN_G3; Fanout = 0; PIN Node = 'freq2_2'
        Info: Total cell delay = 2.642 ns ( 83.50 % )
        Info: Total interconnect delay = 0.522 ns ( 16.50 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Sun Dec 21 15:14:07 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01