freq2_2.map.rpt

奇数分频:2.2倍分频,其他任意奇数倍的分频可扩展得到.

; Allow Any RAM Size For Recognition                           ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                      ;
+----------------------------------+-----------------+-----------+------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path                               ;
+----------------------------------+-----------------+-----------+------------------------------------------------------------+
; freq2_2.v                        ; yes             ; Other     ; D:/EDA/altera/80/quartus/Z_my_project_08/freq2_2/freq2_2.v ;
+----------------------------------+-----------------+-----------+------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 14      ;
;                                             ;         ;
; Total combinational functions               ; 14      ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 8       ;
;     -- 3 input functions                    ; 5       ;
;     -- <=2 input functions                  ; 1       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 14      ;
;     -- arithmetic mode                      ; 0       ;
;                                             ;         ;
; Total registers                             ; 7       ;
;     -- Dedicated logic registers            ; 7       ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 2       ;
; Maximum fan-out node                        ; freq[2] ;
; Maximum fan-out                             ; 8       ;
; Total fan-out                               ; 64      ;
; Average fan-out                             ; 2.78    ;
+---------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |freq2_2                   ; 14 (14)           ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 2    ; 0            ; |freq2_2            ;              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 7     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |freq2_2|freq[0]           ;
; 5:1                ; 3 bits    ; 9 LEs         ; 3 LEs                ; 6 LEs                  ; Yes        ; |freq2_2|count[0]          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sun Dec 21 15:12:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freq2_2 -c freq2_2
Warning: Using design file freq2_2.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: freq2_2
Info: Elaborating entity "freq2_2" for the top level hierarchy
Info: Implemented 16 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 160 megabytes
    Info: Processing ended: Sun Dec 21 15:13:02 2008
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:03