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<a name="1205227"> </a><font color="#003366" face="Verdana, Arial, Helvetica, sans-serif">13.10 Device memory access</font>
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<p>
<a name="1205228"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">In the ST20C2 instruction set there are two classes of memory access instructions, normal accesses and "device" accesses. Device memory accesses behave slightly differently to normal accesses, and it is important to use the right one, especially when accessing peripherals or using a cache.</font>
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<a name="1205229"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">Device accesses are performed using a number of special instructions, collectively referred to as device instructions:</font>
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<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205230"> </a><font size=2 face=Courier><strong>devlb</strong></font> and <font size=2 face=Courier><strong>devsb</strong></font> - read and write a byte of memory,</font></p>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205231"> </a><font size=2 face=Courier><strong>devls</strong></font> and <font size=2 face=Courier><strong>devss</strong></font> - read and write a 16-bit quantity of memory,</font></p>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205232"> </a><font size=2 face=Courier><strong>devlw</strong></font> and <font size=2 face=Courier><strong>devsw</strong></font> - read and write a 32-bit word of memory,</font></p>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205233"> </a><font size=2 face=Courier><strong>devmove</strong></font> - move a block of memory (both source and destination addresses use device accesses).</font></p>
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<a name="1205234"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">All other instructions which read or write to memory generate "normal" memory accesses.</font>
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<a name="1205235"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">A device access has a number of special attributes.</font>
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<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205236"> </a>When accessing the internal peripheral space, device instructions use the peripheral bus rather than the memory bus. All on-chip peripherals within the internal peripheral space are connected to the peripheral bus, so device instructions must be used to access them.</font></p>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205237"> </a>When accessing cacheable memory, device instructions always bypass the cache, and access memory directly. The data accessed is not loaded into the cache. Even if the memory location being accessed has been cached, a device access to that location accesses memory directly, and the data in the cache is not updated.</font></p>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205238"> </a>Device instructions prevent the CPU performing any optimizations which may be unsafe when applied to peripheral registers. In particular, any device writes must complete before the next instruction is executed, while a normal memory write may be buffered.</font></p>
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<a name="1205239"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">In general, there are two cases when a device instruction must be used:</font>
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<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205240"> </a>when accessing on-chip peripherals in the internal peripheral space,</font></p>
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<dt> <a name="1209670"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The address of the internal peripheral space varies between devices, but is usually between <font size=2 face=Courier><strong>0x00000000</strong></font> and <font size=2 face=Courier><strong>0x3fffffff</strong></font> or <font size=2 face=Courier><strong>0x20000000</strong></font> to <font size=2 face=Courier><strong>0x3fffffff</strong></font>.</font>
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<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li ><a name="1205241"> </a>when accessing cacheable memory which should not be loaded into the cache.</font></p>
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<dt> <a name="1209674"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The most common case where this is useful is when memory is written to by a peripheral using DMA. DMA memory accesses are always direct to memory, ignoring the cache. So when the CPU accesses the memory location, it is important it does not read a value from the cache rather than memory. This is because the cache would not be updated when the DMA access was performed and so could contain "stale" or old data.</font>
<dt> <a name="1205242"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">A beneficial side-effect of not caching data in this way is that frequently data written into memory using DMA is read once, immediately written to another location (possibly an output peripheral) and never read again. Thus loading the data into cache would be of no benefit, and would prevent useful data being cached.</font>
<dt> <a name="1205243"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">When using memory in this way it is necessary to be aware of the cache alignment of the data. When a word is read from cacheable memory using a normal memory access instruction, not only the word accessed is brought into the cache, but also the surrounding words, to fill the whole cache line. Later when the cache line is discarded, if any word within the cache line has been written to, the whole cache line is written out into memory. If one of the adjacent words had been written to using a device instruction (or by a peripheral performing DMA) the cache write back would overwrite this word with old data.</font>
<dt> <a name="1205244"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The easiest way to avoid this problem is to ensure that all buffers accessed using device instructions are aligned to the size of a cache line, and are extended so their size is a multiple of the cache line size. The alignment can be achieved by placing the buffer in a named section, and then use the <font size=2 face=Courier><strong>alignment </strong></font>option to the <font size=2 face=Courier><strong>place</strong></font> command.</font>
<dt> <a name="1205245"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">(An alternative to using device instructions to bypass the cache is to use the "cacheability control" registers of the cache to reset the device hardware. See the appropriate device datasheet for details. This allows entire blocks of memory to be marked as "not cacheable" and access is then performed using normal memory access).</font>
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<p>
<a name="1205246"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">A memory location should always be accessed using only device or non-device instructions, never a mixture of the two. Failure to follow this rule can lead to some very hard-to-diagnose problems.</font>
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