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<title>11.3 Analyze</title>

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<h2>
  <a name="1205699"> </a><font color="#003366"  face="Verdana, Arial, Helvetica, sans-serif">11.3 	 Analyze</font>
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<p>
  <a name="1205700"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The <span class=Signal>Analyse</span> pin exists in order that the state of an ST20-C2 system can be investigated. This is achieved by bringing the system to a halt in such a way that the state of the processor can be examined. </font>
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<p>
  <a name="1204737"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The state of the processes executing on an analyzed ST20-C2 can be examined. The processes in the active set are found in the linked lists holding the process queues. The processes waiting on the timers, along with the time they are waiting for, are found in the linked stack holding the timer queues. Processes waiting for communication can be found by examining the channel control words. </font>
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<p>
  <a name="1204738"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The <span class=Signal>Analyse</span> pin is asserted which causes the system to come to a halt after a specifiable time. The <span class=Signal>Reset</span> pin is then asserted while continuing to assert the <span class=Signal>Analyse</span> pin, for at least the specified Reset hold time, and is then taken low, while still asserting the <span class=Signal>Analyse</span> pin. The <span class=Signal>Analyse</span> pin is then de-asserted and the processor boots. </font>
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<p>
  <a name="1204739"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The components of an ST20-C2 system respond to the assertion of <span class=Signal>Analyse</span> in the manner shown in <a href="boot4.htm#1204772"><font  color="#0000ff" face="Verdana, Arial, Helvetica, sans-serif"><i>Table

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