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<h2>
<a name="1205659"> </a><font color="#003366" face="Verdana, Arial, Helvetica, sans-serif">9.2 Interrupt controller</font>
</h2><hr>
<p>
<a name="1205796"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The following information is for general guidance only as the interrupt controller is not part of the CPU and therefore may vary between different applications. Details of the interrupt controller for a specific implementation are found in that product's datasheet. The details given in the following sections concerning interrupt pending, executing and mask bits are an example of one possible interrupt controller implementation.</font>
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<p>
<a name="1205801"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">From the CPU perspective, it sees the interrupt controller only via an interface that presents an interrupt request along with an associated workspace descriptor with signals to indicate to the interrupt controller when it accepts an interrupt and when it completes an interrupt. </font>
</p>
<p>
<a name="1205881"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">Interrupts on the ST20-C2 are implemented via an interrupt controller peripheral. It differs from other internal peripherals in that it can signal to the CPU to switch to a new process.</font>
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<p>
<a name="1205807"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The interrupt controller is responsible for receiving interrupts, handling their prioritization and sending interrupt requests to the ST20-C2 CPU. From the processor's perspective all it sees is a request to take an interrupt which immediately pre-empts existing execution at the processor priority of the interrupt, because of this it is possible that different uses of the ST20-C2 use different interrupt controller peripherals. The descriptions that follow assume an interrupt controller that is broadly similar to the one used with the initial application devices using the ST20-C2 (for full details of the interrupt controller on a particular device please refer to its datasheet).</font>
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<p>
<a name="1205815"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The interrupt controller contains a vector of pointers to interrupt handlers. Each interrupt handler is represented by its workspace descriptor, this consists of the workspace pointer and the processor priority of the interrupt handler. The instruction pointer for the handler and other data are then found in the workspace. The controller contains a workspace pointer for each level of interrupt. These interrupts are ordered so that higher levels of interrupt pre-empt lower levels.</font>
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<p>
<a name="1205821"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif"><em>Note: High priority interrupts must be placed at higher interrupt levels than any low priority interrupt, and low priority interrupts must be placed at lower levels than any high priority interrupt. There is no hardware to check this and if this is violated then the resulting behavior may become unpredictable.</em></font>
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<p>
<a name="1205825"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">An interrupt can be signalled to the controller via a signal on an external pin, a signal directly wired from an internal peripheral or subsystem, or via software asserting an interrupt in a bit mask. The connections to external pins and internal wires are allocated to set interrupt levels in each ST20-C2 variant (details of this allocation are in the relevant datasheet). The triggering condition for each interrupt can be individually set by software to allow for edge, level or transition triggering of interrupts. Interrupts can be individually enabled or disabled by setting or clearing bits in a mask word in the interrupt controller.</font>
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<h3>
<a name="1205832"> </a><font color="#003366" face="Verdana, Arial, Helvetica, sans-serif">Interrupt controller behavior over interrupts</font>
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<p>
<a name="1205833"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">When the interrupt controller receives an interrupt signal the following sequence of events occurs.</font>
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<ol type="1">
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li value="1"><a name="1205835"> </a>The bit for this interrupt level is set in the interrupt pending register to indicate that there is an interrupt to be serviced at this level.</font></p>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li value="2"><a name="1205945"> </a>Every cycle the controller tests to see if there is an interrupt which is pending, is enabled and is of a higher priority than any interrupt currently executing.</font></p>
<dl>
<dt> <a name="1205952"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">If this is the case then the controller signals the interrupt to the CPU along with the associated workspace descriptor.</font>
</dl>
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<p>
<a name="1205961"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif"><em>Note: The interrupt controller signals the highest priority pending enabled interrupt so that if while waiting for a response from the CPU a higher level of interrupt becomes pending, the new descriptor is substituted for the existing one.</em></font>
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<ol type="1">
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li value="3"><a name="1205964"> </a>The CPU (eventually) accepts this request and starts to run the interrupt handler. If the descriptor indicates a low priority interrupt then this acceptance is delayed until no high priority process is running.</font></p>
<dl>
<dt> <a name="1206034"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">When the CPU accepts the request it is then guaranteed to execute this interrupt. The interrupt controller reflects this by setting the relevant bit in the interrupt executing register and clears the interrupt pending bit.</font>
</dl>
<p> <font size=2 face="Verdana, Arial, Helvetica, sans-serif"><li value="4"><a name="1205970"> </a>At some point in the future the CPU completes the interrupt and signals this to the interrupt controller.</font></p>
<dl>
<dt> <a name="1205972"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The controller knows that this signal is coming from the highest currently executing interrupt so clears the interrupt executing bit.</font>
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<h3>
<a name="1205974"> </a><font color="#003366" face="Verdana, Arial, Helvetica, sans-serif">CPU behavior over interrupts</font>
</h3>
<p>
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