seq_op14.htm

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  <a name="1206426"> </a><font color="#003366"  face="Verdana, Arial, Helvetica, sans-serif">6.13 	 Device access instructions</font>
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<p>
  <a name="1206427"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The previously described memory access instructions use the following memory model: a read instruction applied to a particular location returns the last value written to that location by a write instruction. This says nothing about whether the value is actually stored in main memory by the write, nor does it say anything about the temporal order of reading and writing in relation to other instructions.</font>
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<p>
  <a name="1206428"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">If the memory system contains a cache then it is possible that data written to a cached address may not get written back to main memory before a subsequent access to the same address. This means, for example, in a sequence where a read is made between two writes to the same location:</font>
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  <a name="1206429"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif"><strong>ldc A; ldl Location1; stnl 0;</strong>

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