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<title>9.4 Configuration of the interrupt controller</title>

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<h2>
  <a name="1204575"> </a><font color="#003366"  face="Verdana, Arial, Helvetica, sans-serif">9.4 	 Configuration of the interrupt controller</font>
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<p>
  <a name="1204576"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The following information is for general guidance only as the interrupt controller is not part of the CPU and thus may vary between different applications, refer to the datasheet for the specific application chip being used for the definition of the registers in the Interrupt Controller. This section describes an interrupt controller similar to those implemented on the first application devices using the ST20-C2.</font>
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  <a name="1204577"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">The interrupt controller provided with current applications devices using the ST20-C2 supports a maximum of 16 levels of interrupt, though for some variants this has been reduced further to reduce the area required by the controller.</font>
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<p>
  <a name="1204578"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">For configuration purposes, the interrupt controller looks like any other internal peripheral. It is allocated a 4燢byte block of memory in the internal peripheral address space from <span class=Signal>InterruptControllerBase</span>. Currently this space has been fixed at the start of this area at 0x20000000. The registers in this address space can be accessed using <strong>devlw</strong> and <strong>devsw</strong>.</font>
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  <a name="1204579"> </a><font size=2  face="Verdana, Arial, Helvetica, sans-serif">Inside this area information is stored at the offsets from <span class=Signal>InterruptControllerBase</span> shown in <a href="interru5.htm#1204610"><font  color="#0000ff" face="Verdana, Arial, Helvetica, sans-serif"><i>Table

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