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<a name="1204415"> </a><font color="#003366" face="Verdana, Arial, Helvetica, sans-serif">12.1 Introduction</font>
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<a name="1204416"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">All ST20 processors that support cache use similar hardware and the operation of the caches is the same, however, the blocks of memory that can be cached vary between ST20 devices; see the appropriate device datasheets for details.</font>
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<a name="1204417"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">The ST20 cache system provides a read-only instruction cache and a write-back data cache.</font>
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<a name="1204418"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">There is a risk when using cache that the cache can become incoherent with main memory, meaning that the contents of the cache conflicts with the contents of main memory. For example, devices that perform direct memory access (DMA) modify the main memory without updating the cache, leaving its contents invalid. For this reason enabling the data cache for blocks of memory accessed by the DMA engine is not recommended.</font>
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<a name="1205173"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif"><em>Note: On an ST20C2 core, device access instructions (generated with <font size=2 face=Courier><strong>#pragma ST_device</strong></font>) bypass the cache and can be used to solve some cache coherency issues.</em></font>
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<a name="1204419"> </a><font color="#003366" face="Verdana, Arial, Helvetica, sans-serif">12.1.1 Data caches with internal SRAM</font>
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<a name="1206011"> </a><font size=2 face="Verdana, Arial, Helvetica, sans-serif">Some ST20 devices have a data cache which must be reserved by the linker in order to prevent it from being corrupted by the application. This is described in the <em>ST20 Embedded Toolset User Manual</em>, chapter <em>Defining a target system</em>.</font>
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<font size=1 face="Verdana, Arial, Helvetica, sans-serif"> © 2001, 2002, 2003 STMicroelectronics. All Rights Reserved.<br>
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