📄 i86.c
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}
static void i_test_wr16(void) /* Opcode 0x85 */
{
DEF_wr16(dst,src);
cycle_count-=3;
ANDW(dst,src);
}
static void i_xchg_br8(void) /* Opcode 0x86 */
{
DEF_br8(dst,src);
cycle_count-=4;
RegByte(ModRM)=dst;
PutbackRMByte(ModRM,src);
}
static void i_xchg_wr16(void) /* Opcode 0x87 */
{
DEF_wr16(dst,src);
cycle_count-=4;
RegWord(ModRM)=dst;
PutbackRMWord(ModRM,src);
}
static void i_mov_br8(void) /* Opcode 0x88 */
{
unsigned ModRM = FETCH;
BYTE src = RegByte(ModRM);
cycle_count-=2;
PutRMByte(ModRM,src);
}
static void i_mov_wr16(void) /* Opcode 0x89 */
{
unsigned ModRM = FETCH;
WORD src = RegWord(ModRM);
cycle_count-=2;
PutRMWord(ModRM,src);
}
static void i_mov_r8b(void) /* Opcode 0x8a */
{
unsigned ModRM = FETCH;
BYTE src = GetRMByte(ModRM);
cycle_count-=2;
RegByte(ModRM)=src;
}
static void i_mov_r16w(void) /* Opcode 0x8b */
{
unsigned ModRM = FETCH;
WORD src = GetRMWord(ModRM);
cycle_count-=2;
RegWord(ModRM)=src;
}
static void i_mov_wsreg(void) /* Opcode 0x8c */
{
unsigned ModRM = FETCH;
cycle_count-=2;
PutRMWord(ModRM,sregs[(ModRM & 0x38) >> 3]);
}
static void i_lea(void) /* Opcode 0x8d */
{
unsigned ModRM = FETCH;
cycle_count-=2;
RegWord(ModRM)=(*GetEA[ModRM])();
}
static void i_mov_sregw(void) /* Opcode 0x8e */
{
unsigned ModRM = FETCH;
WORD src = GetRMWord(ModRM);
cycle_count-=2;
switch (ModRM & 0x38)
{
case 0x00: /* mov es,ew */
sregs[ES] = src;
base[ES] = SegBase(ES);
break;
case 0x18: /* mov ds,ew */
sregs[DS] = src;
base[DS] = SegBase(DS);
break;
case 0x10: /* mov ss,ew */
sregs[SS] = src;
base[SS] = SegBase(SS); /* no interrupt allowed before next instr */
instruction[FETCH]();
break;
case 0x08: /* mov cs,ew */
break; /* doesn't do a jump far */
}
}
static void i_popw(void) /* Opcode 0x8f */
{
unsigned ModRM = FETCH;
WORD tmp;
POP(tmp);
cycle_count-=4;
PutRMWord(ModRM,tmp);
}
#define XchgAXReg(Reg) \
{ \
WORD tmp; \
tmp = regs.w[Reg]; \
regs.w[Reg] = regs.w[AX]; \
regs.w[AX] = tmp; \
cycle_count-=3; \
}
static void i_nop(void) /* Opcode 0x90 */
{
/* this is XchgAXReg(AX); */
cycle_count-=3;
}
static void i_xchg_axcx(void) /* Opcode 0x91 */
{
XchgAXReg(CX);
}
static void i_xchg_axdx(void) /* Opcode 0x92 */
{
XchgAXReg(DX);
}
static void i_xchg_axbx(void) /* Opcode 0x93 */
{
XchgAXReg(BX);
}
static void i_xchg_axsp(void) /* Opcode 0x94 */
{
XchgAXReg(SP);
}
static void i_xchg_axbp(void) /* Opcode 0x95 */
{
XchgAXReg(BP);
}
static void i_xchg_axsi(void) /* Opcode 0x96 */
{
XchgAXReg(SI);
}
static void i_xchg_axdi(void) /* Opcode 0x97 */
{
XchgAXReg(DI);
}
static void i_cbw(void) /* Opcode 0x98 */
{
cycle_count-=2;
regs.b[AH] = (regs.b[AL] & 0x80) ? 0xff : 0;
}
static void i_cwd(void) /* Opcode 0x99 */
{
cycle_count-=5;
regs.w[DX] = (regs.b[AH] & 0x80) ? 0xffff : 0;
}
static void i_call_far(void)
{
unsigned tmp, tmp2;
tmp = FETCH;
tmp += FETCH << 8;
tmp2 = FETCH;
tmp2 += FETCH << 8;
PUSH(sregs[CS]);
PUSH(ip);
ip = (WORD)tmp;
sregs[CS] = (WORD)tmp2;
base[CS] = SegBase(CS);
cycle_count-=14;
}
static void i_wait(void) /* Opcode 0x9b */
{
cycle_count-=4;
}
static void i_pushf(void) /* Opcode 0x9c */
{
cycle_count-=3;
PUSH( CompressFlags() | 0xf000 );
}
static void i_popf(void) /* Opcode 0x9d */
{
unsigned tmp;
POP(tmp);
cycle_count-=2;
ExpandFlags(tmp);
if (TF) trap();
}
static void i_sahf(void) /* Opcode 0x9e */
{
unsigned tmp = (CompressFlags() & 0xff00) | (regs.b[AH] & 0xd5);
ExpandFlags(tmp);
}
static void i_lahf(void) /* Opcode 0x9f */
{
regs.b[AH] = CompressFlags() & 0xff;
cycle_count-=4;
}
static void i_mov_aldisp(void) /* Opcode 0xa0 */
{
unsigned addr;
addr = FETCH;
addr += FETCH << 8;
cycle_count-=4;
regs.b[AL] = GetMemB(DS, addr);
}
static void i_mov_axdisp(void) /* Opcode 0xa1 */
{
unsigned addr;
addr = FETCH;
addr += FETCH << 8;
cycle_count-=4;
regs.b[AL] = GetMemB(DS, addr);
regs.b[AH] = GetMemB(DS, addr+1);
}
static void i_mov_dispal(void) /* Opcode 0xa2 */
{
unsigned addr;
addr = FETCH;
addr += FETCH << 8;
cycle_count-=3;
PutMemB(DS, addr, regs.b[AL]);
}
static void i_mov_dispax(void) /* Opcode 0xa3 */
{
unsigned addr;
addr = FETCH;
addr += FETCH << 8;
cycle_count-=3;
PutMemB(DS, addr, regs.b[AL]);
PutMemB(DS, addr+1, regs.b[AH]);
}
static void i_movsb(void) /* Opcode 0xa4 */
{
BYTE tmp = GetMemB(DS,regs.w[SI]);
PutMemB(ES,regs.w[DI], tmp);
regs.w[DI] += -2*DF +1;
regs.w[SI] += -2*DF +1;
cycle_count-=5;
}
static void i_movsw(void) /* Opcode 0xa5 */
{
WORD tmp = GetMemW(DS,regs.w[SI]);
PutMemW(ES,regs.w[DI], tmp);
regs.w[DI] += -4*DF +2;
regs.w[SI] += -4*DF +2;
cycle_count-=5;
}
static void i_cmpsb(void) /* Opcode 0xa6 */
{
unsigned dst = GetMemB(ES, regs.w[DI]);
unsigned src = GetMemB(DS, regs.w[SI]);
SUBB(src,dst); /* opposite of the usual convention */
regs.w[DI] += -2*DF +1;
regs.w[SI] += -2*DF +1;
cycle_count-=10;
}
static void i_cmpsw(void) /* Opcode 0xa7 */
{
unsigned dst = GetMemW(ES, regs.w[DI]);
unsigned src = GetMemW(DS, regs.w[SI]);
SUBW(src,dst); /* opposite of the usual convention */
regs.w[DI] += -4*DF +2;
regs.w[SI] += -4*DF +2;
cycle_count-=10;
}
static void i_test_ald8(void) /* Opcode 0xa8 */
{
DEF_ald8(dst,src);
cycle_count-=4;
ANDB(dst,src);
}
static void i_test_axd16(void) /* Opcode 0xa9 */
{
DEF_axd16(dst,src);
cycle_count-=4;
ANDW(dst,src);
}
static void i_stosb(void) /* Opcode 0xaa */
{
PutMemB(ES,regs.w[DI],regs.b[AL]);
regs.w[DI] += -2*DF +1;
cycle_count-=4;
}
static void i_stosw(void) /* Opcode 0xab */
{
PutMemB(ES,regs.w[DI],regs.b[AL]);
PutMemB(ES,regs.w[DI]+1,regs.b[AH]);
regs.w[DI] += -4*DF +2;
cycle_count-=4;
}
static void i_lodsb(void) /* Opcode 0xac */
{
regs.b[AL] = GetMemB(DS,regs.w[SI]);
regs.w[SI] += -2*DF +1;
cycle_count-=6;
}
static void i_lodsw(void) /* Opcode 0xad */
{
regs.w[AX] = GetMemW(DS,regs.w[SI]);
regs.w[SI] += -4*DF+2;
cycle_count-=6;
}
static void i_scasb(void) /* Opcode 0xae */
{
unsigned src = GetMemB(ES, regs.w[DI]);
unsigned dst = regs.b[AL];
SUBB(dst,src);
regs.w[DI] += -2*DF +1;
cycle_count-=9;
}
static void i_scasw(void) /* Opcode 0xaf */
{
unsigned src = GetMemW(ES, regs.w[DI]);
unsigned dst = regs.w[AX];
SUBW(dst,src);
regs.w[DI] += -4*DF +2;
cycle_count-=9;
}
static void i_mov_ald8(void) /* Opcode 0xb0 */
{
regs.b[AL] = FETCH;
cycle_count-=4;
}
static void i_mov_cld8(void) /* Opcode 0xb1 */
{
regs.b[CL] = FETCH;
cycle_count-=4;
}
static void i_mov_dld8(void) /* Opcode 0xb2 */
{
regs.b[DL] = FETCH;
cycle_count-=4;
}
static void i_mov_bld8(void) /* Opcode 0xb3 */
{
regs.b[BL] = FETCH;
cycle_count-=4;
}
static void i_mov_ahd8(void) /* Opcode 0xb4 */
{
regs.b[AH] = FETCH;
cycle_count-=4;
}
static void i_mov_chd8(void) /* Opcode 0xb5 */
{
regs.b[CH] = FETCH;
cycle_count-=4;
}
static void i_mov_dhd8(void) /* Opcode 0xb6 */
{
regs.b[DH] = FETCH;
cycle_count-=4;
}
static void i_mov_bhd8(void) /* Opcode 0xb7 */
{
regs.b[BH] = FETCH;
cycle_count-=4;
}
static void i_mov_axd16(void) /* Opcode 0xb8 */
{
regs.b[AL] = FETCH;
regs.b[AH] = FETCH;
cycle_count-=4;
}
static void i_mov_cxd16(void) /* Opcode 0xb9 */
{
regs.b[CL] = FETCH;
regs.b[CH] = FETCH;
cycle_count-=4;
}
static void i_mov_dxd16(void) /* Opcode 0xba */
{
regs.b[DL] = FETCH;
regs.b[DH] = FETCH;
cycle_count-=4;
}
static void i_mov_bxd16(void) /* Opcode 0xbb */
{
regs.b[BL] = FETCH;
regs.b[BH] = FETCH;
cycle_count-=4;
}
static void i_mov_spd16(void) /* Opcode 0xbc */
{
regs.b[SPL] = FETCH;
regs.b[SPH] = FETCH;
cycle_count-=4;
}
static void i_mov_bpd16(void) /* Opcode 0xbd */
{
regs.b[BPL] = FETCH;
regs.b[BPH] = FETCH;
cycle_count-=4;
}
static void i_mov_sid16(void) /* Opcode 0xbe */
{
regs.b[SIL] = FETCH;
regs.b[SIH] = FETCH;
cycle_count-=4;
}
static void i_mov_did16(void) /* Opcode 0xbf */
{
regs.b[DIL] = FETCH;
regs.b[DIH] = FETCH;
cycle_count-=4;
}
void rotate_shift_Byte(unsigned ModRM, unsigned count)
{
unsigned src = (unsigned)GetRMByte(ModRM);
unsigned dst=src;
if (count==0)
{
cycle_count-=8; /* or 7 if dest is in memory */
}
else if (count==1)
{
cycle_count-=2;
switch (ModRM & 0x38)
{
case 0x00: /* ROL eb,1 */
CarryVal = src & 0x80;
dst=(src<<1)+CF;
PutbackRMByte(ModRM,dst);
OverVal = (src^dst)&0x80;
break;
case 0x08: /* ROR eb,1 */
CarryVal = src & 0x01;
dst = ((CF<<8)+src) >> 1;
PutbackRMByte(ModRM,dst);
OverVal = (src^dst)&0x80;
break;
case 0x10: /* RCL eb,1 */
dst=(src<<1)+CF;
PutbackRMByte(ModRM,dst);
SetCFB(dst);
OverVal = (src^dst)&0x80;
break;
case 0x18: /* RCR eb,1 */
dst = ((CF<<8)+src) >> 1;
PutbackRMByte(ModRM,dst);
CarryVal = src & 0x01;
OverVal = (src^dst)&0x80;
break;
case 0x20: /* SHL eb,1 */
case 0x30:
dst = src << 1;
PutbackRMByte(ModRM,dst);
SetCFB(dst);
OverVal = (src^dst)&0x80;
AuxVal = 1;
SetSZPF_Byte(dst);
break;
case 0x28: /* SHR eb,1 */
dst = src >> 1;
PutbackRMByte(ModRM,dst);
CarryVal = src & 0x01;
OverVal = src & 0x80;
AuxVal = 1;
SetSZPF_Byte(dst);
break;
case 0x38: /* SAR eb,1 */
dst = ((INT8)src) >> 1;
PutbackRMByte(ModRM,dst);
CarryVal = src & 0x01;
OverVal = 0;
AuxVal = 1;
SetSZPF_Byte(dst);
break;
}
}
else
{
cycle_count-=8+4*count; /* or 7+4*count if dest is in memory */
switch (ModRM & 0x38)
{
case 0x00: /* ROL eb,count */
for (; count > 0; count--)
{
CarryVal = dst & 0x80;
dst = (dst << 1) + CF;
}
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x08: /* ROR eb,count */
for (; count > 0; count--)
{
CarryVal = dst & 0x01;
dst = (dst >> 1) + (CF << 7);
}
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x10: /* RCL eb,count */
for (; count > 0; count--)
{
dst = (dst << 1) + CF;
SetCFB(dst);
}
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x18: /* RCR eb,count */
for (; count > 0; count--)
{
dst = (CF<<8)+dst;
CarryVal = dst & 0x01;
dst >>= 1;
}
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x20:
case 0x30: /* SHL eb,count */
dst <<= count;
SetCFB(dst);
AuxVal = 1;
SetSZPF_Byte(dst);
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x28: /* SHR eb,count */
dst >>= count-1;
CarryVal = dst & 0x1;
dst >>= 1;
SetSZPF_Byte(dst);
AuxVal = 1;
PutbackRMByte(ModRM,(BYTE)dst);
break;
case 0x38: /* SAR eb,count */
dst = ((INT8)dst) >> (count-1);
CarryVal = dst & 0x1;
dst = ((INT8)((BYTE)dst)) >> 1;
SetSZPF_Byte(dst);
AuxVal = 1;
PutbackRMByte(ModRM,(BYTE)dst);
break;
}
}
}
void rotate_shift_Word(unsigned ModRM, unsigned count)
{
unsigned src = GetRMWord(ModRM);
unsigned dst=src;
if (count==0)
{
cycle_count-=8; /* or 7 if dest is in memory */
}
else if (count==1)
{
cycle_count-=2;
switch (ModRM & 0x38)
{
#if 0
case 0x00: /* ROL ew,1 */
tmp2 = (tmp << 1) + CF;
SetCFW(tmp2);
OverVal = !(!(tmp & 0x4000)) != CF;
PutbackRMWord(ModRM,tmp2);
break;
case 0x08: /* ROR ew,1 */
CarryVal = tmp & 0x01;
tmp2 = (tmp >> 1) + ((unsigned)CF << 15);
OverVal = !(!(tmp & 0x8000)) != CF;
PutbackRMWord(ModRM,tmp2);
break;
case 0x10: /* RCL ew,1 */
tmp2 = (tmp << 1) + CF;
SetCFW(tmp2);
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