i86.c

这个是延伸mame的在wince平台下的游戏模拟器的代码

static void i_cmp_ald8(void)    /* Opcode 0x3c */
{
    DEF_ald8(dst,src);
    cycle_count-=4;
    SUBB(dst,src);
}

static void i_cmp_axd16(void)    /* Opcode 0x3d */
{
    DEF_axd16(dst,src);
    cycle_count-=4;
    SUBW(dst,src);
}

static void i_ds(void)    /* Opcode 0x3e */
{
    seg_prefix=TRUE;
    prefix_base=base[DS];
    cycle_count-=2;
    instruction[FETCH]();
}

static void i_aas(void)    /* Opcode 0x3f */
{
    if (AF || ((regs.b[AL] & 0xf) > 9))
    {
	regs.b[AL] -= 6;
	regs.b[AH] -= 1;
	AuxVal = 1;
	CarryVal = 1;
    }
    else {
	AuxVal = 0;
	CarryVal = 0;
    }
    regs.b[AL] &= 0x0F;
    cycle_count-=8;
}

#define IncWordReg(Reg) \
{ \
    unsigned tmp = (unsigned)regs.w[Reg]; \
    unsigned tmp1 = tmp+1; \
    SetOFW_Add(tmp1,tmp,1); \
    SetAF(tmp1,tmp,1); \
    SetSZPF_Word(tmp1); \
    regs.w[Reg]=tmp1; \
    cycle_count-=3; \
}

static void i_inc_ax(void)    /* Opcode 0x40 */
{
    IncWordReg(AX);
}

static void i_inc_cx(void)    /* Opcode 0x41 */
{
    IncWordReg(CX);
}

static void i_inc_dx(void)    /* Opcode 0x42 */
{
    IncWordReg(DX);
}

static void i_inc_bx(void)    /* Opcode 0x43 */
{
    IncWordReg(BX);
}

static void i_inc_sp(void)    /* Opcode 0x44 */
{
    IncWordReg(SP);
}

static void i_inc_bp(void)    /* Opcode 0x45 */
{
    IncWordReg(BP);
}

static void i_inc_si(void)    /* Opcode 0x46 */
{
    IncWordReg(SI);
}

static void i_inc_di(void)    /* Opcode 0x47 */
{
    IncWordReg(DI);
}

#define DecWordReg(Reg) \
{ \
    unsigned tmp = (unsigned)regs.w[Reg]; \
    unsigned tmp1 = tmp-1; \
    SetOFW_Sub(tmp1,1,tmp); \
    SetAF(tmp1,tmp,1); \
    SetSZPF_Word(tmp1); \
    regs.w[Reg]=tmp1; \
    cycle_count-=3; \
}

static void i_dec_ax(void)    /* Opcode 0x48 */
{
    DecWordReg(AX);
}

static void i_dec_cx(void)    /* Opcode 0x49 */
{
    DecWordReg(CX);
}

static void i_dec_dx(void)    /* Opcode 0x4a */
{
    DecWordReg(DX);
}

static void i_dec_bx(void)    /* Opcode 0x4b */
{
    DecWordReg(BX);
}

static void i_dec_sp(void)    /* Opcode 0x4c */
{
    DecWordReg(SP);
}

static void i_dec_bp(void)    /* Opcode 0x4d */
{
    DecWordReg(BP);
}

static void i_dec_si(void)    /* Opcode 0x4e */
{
    DecWordReg(SI);
}

static void i_dec_di(void)    /* Opcode 0x4f */
{
    DecWordReg(DI);
}

static void i_push_ax(void)    /* Opcode 0x50 */
{
    cycle_count-=4;
    PUSH(regs.w[AX]);
}

static void i_push_cx(void)    /* Opcode 0x51 */
{
    cycle_count-=4;
    PUSH(regs.w[CX]);
}

static void i_push_dx(void)    /* Opcode 0x52 */
{
    cycle_count-=4;
    PUSH(regs.w[DX]);
}

static void i_push_bx(void)    /* Opcode 0x53 */
{
    cycle_count-=4;
    PUSH(regs.w[BX]);
}

static void i_push_sp(void)    /* Opcode 0x54 */
{
    cycle_count-=4;
    PUSH(regs.w[SP]);
}

static void i_push_bp(void)    /* Opcode 0x55 */
{
    cycle_count-=4;
    PUSH(regs.w[BP]);
}


static void i_push_si(void)    /* Opcode 0x56 */
{
    cycle_count-=4;
    PUSH(regs.w[SI]);
}

static void i_push_di(void)    /* Opcode 0x57 */
{
    cycle_count-=4;
    PUSH(regs.w[DI]);
}

static void i_pop_ax(void)    /* Opcode 0x58 */
{
    cycle_count-=2;
    POP(regs.w[AX]);
}

static void i_pop_cx(void)    /* Opcode 0x59 */
{
    cycle_count-=2;
    POP(regs.w[CX]);
}

static void i_pop_dx(void)    /* Opcode 0x5a */
{
    cycle_count-=2;
    POP(regs.w[DX]);
}

static void i_pop_bx(void)    /* Opcode 0x5b */
{
    cycle_count-=2;
    POP(regs.w[BX]);
}

static void i_pop_sp(void)    /* Opcode 0x5c */
{
    cycle_count-=2;
    POP(regs.w[SP]);
}

static void i_pop_bp(void)    /* Opcode 0x5d */
{
    cycle_count-=2;
    POP(regs.w[BP]);
}

static void i_pop_si(void)    /* Opcode 0x5e */
{
    cycle_count-=2;
    POP(regs.w[SI]);
}

static void i_pop_di(void)    /* Opcode 0x5f */
{
    cycle_count-=2;
    POP(regs.w[DI]);
}

static void i_pusha(void)    /* Opcode 0x60 */
{
    unsigned tmp=regs.w[SP];
    cycle_count-=17;
    PUSH(regs.w[AX]);
    PUSH(regs.w[CX]);
    PUSH(regs.w[DX]);
    PUSH(regs.w[BX]);
    PUSH(tmp);
    PUSH(regs.w[BP]);
    PUSH(regs.w[SI]);
    PUSH(regs.w[DI]);
}

static void i_popa(void)    /* Opcode 0x61 */
{
    unsigned tmp;
    cycle_count-=19;
    POP(regs.w[DI]);
    POP(regs.w[SI]);
    POP(regs.w[BP]);
    POP(tmp);
    POP(regs.w[BX]);
    POP(regs.w[DX]);
    POP(regs.w[CX]);
    POP(regs.w[AX]);
}

static void i_bound(void)    /* Opcode 0x62 */
{
    unsigned ModRM = FETCH;
    int low = (INT16)GetRMWord(ModRM);
    int high= (INT16)GetnextRMWord;
    int tmp= (INT16)RegWord(ModRM);
    if (tmp<low || tmp>high) {
        ip-=2;
        I86_interrupt(5);
    }
}

static void i_push_d16(void)    /* Opcode 0x68 */
{
    unsigned tmp = FETCH;
    cycle_count-=3;
    tmp += FETCH << 8;
    PUSH(tmp);
}

static void i_imul_d16(void)    /* Opcode 0x69 */
{
    DEF_r16w(dst,src);
    unsigned src2=FETCH;
    src+=(FETCH<<8);

    cycle_count-=150;
    dst = (INT32)((INT16)src)*(INT32)((INT16)src2);
    CarryVal = OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
    RegWord(ModRM)=(WORD)dst;
}


static void i_push_d8(void)    /* Opcode 0x6a */
{
    unsigned tmp = (WORD)((INT16)((INT8)FETCH));
    cycle_count-=3;
    PUSH(tmp);
}

static void i_imul_d8(void)    /* Opcode 0x6b */
{
    DEF_r16w(dst,src);
    unsigned src2= (WORD)((INT16)((INT8)FETCH));

    cycle_count-=150;
    dst = (INT32)((INT16)src)*(INT32)((INT16)src2);
    CarryVal = OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
    RegWord(ModRM)=(WORD)dst;
}

static void i_insb(void)    /* Opcode 0x6c */
{
    cycle_count-=5;
    PutMemB(ES,regs.w[DI],read_port(regs.w[DX]));
    regs.w[DI]+= -2*DF+1;
}

static void i_insw(void)    /* Opcode 0x6d */
{
    cycle_count-=5;
    PutMemB(ES,regs.w[DI],read_port(regs.w[DX]));
    PutMemB(ES,regs.w[DI]+1,read_port(regs.w[DX]+1));
    regs.w[DI]+= -4*DF+2;
}

static void i_outsb(void)    /* Opcode 0x6e */
{
    cycle_count-=5;
    write_port(regs.w[DX],GetMemB(DS,regs.w[SI]));
    regs.w[DI]+= -2*DF+1;
}

static void i_outsw(void)    /* Opcode 0x6f */
{
    cycle_count-=5;
    write_port(regs.w[DX],GetMemB(DS,regs.w[SI]));
    write_port(regs.w[DX]+1,GetMemB(DS,regs.w[SI]+1));
    regs.w[DI]+= -4*DF+2;
}

static void i_jo(void)    /* Opcode 0x70 */
{
    int tmp = (int)((INT8)FETCH);
    if (OF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jno(void)    /* Opcode 0x71 */
{
    int tmp = (int)((INT8)FETCH);
    if (!OF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jb(void)    /* Opcode 0x72 */
{
    int tmp = (int)((INT8)FETCH);
    if (CF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jnb(void)    /* Opcode 0x73 */
{
    int tmp = (int)((INT8)FETCH);
    if (!CF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jz(void)    /* Opcode 0x74 */
{
    int tmp = (int)((INT8)FETCH);
    if (ZF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jnz(void)    /* Opcode 0x75 */
{
    int tmp = (int)((INT8)FETCH);
    if (!ZF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jbe(void)    /* Opcode 0x76 */
{
    int tmp = (int)((INT8)FETCH);
    if (CF || ZF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jnbe(void)    /* Opcode 0x77 */
{
    int tmp = (int)((INT8)FETCH);
    if (!(CF || ZF)) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_js(void)    /* Opcode 0x78 */
{
    int tmp = (int)((INT8)FETCH);
    if (SF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jns(void)    /* Opcode 0x79 */
{
    int tmp = (int)((INT8)FETCH);
    if (!SF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jp(void)    /* Opcode 0x7a */
{
    int tmp = (int)((INT8)FETCH);
    if (PF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jnp(void)    /* Opcode 0x7b */
{
    int tmp = (int)((INT8)FETCH);
    if (!PF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jl(void)    /* Opcode 0x7c */
{
    int tmp = (int)((INT8)FETCH);
    if ((SF!=OF)&&!ZF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jnl(void)    /* Opcode 0x7d */
{
    int tmp = (int)((INT8)FETCH);
    if (ZF||(SF==OF)) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jle(void)    /* Opcode 0x7e */
{
    int tmp = (int)((INT8)FETCH);
    if (ZF||(SF!=OF)) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_jnle(void)    /* Opcode 0x7f */
{
    int tmp = (int)((INT8)FETCH);
    if ((SF==OF)&&!ZF) {
	ip = (WORD)(ip+tmp);
	cycle_count-=16;
    } else cycle_count-=4;
}

static void i_80pre(void)    /* Opcode 0x80 */
{
    unsigned ModRM = FETCH;
    unsigned dst = GetRMByte(ModRM);
    unsigned src = FETCH;
    cycle_count-=4;

    switch (ModRM & 0x38)
    {
    case 0x00:  /* ADD eb,d8 */
        ADDB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x08:  /* OR eb,d8 */
        ORB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x10:  /* ADC eb,d8 */
        src+=CF;
        ADDB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x18:  /* SBB eb,b8 */
        src+=CF;
        SUBB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x20:  /* AND eb,d8 */
        ANDB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x28:  /* SUB eb,d8 */
        SUBB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x30:  /* XOR eb,d8 */
        XORB(dst,src);
        PutbackRMByte(ModRM,dst);
	break;
    case 0x38:  /* CMP eb,d8 */
        SUBB(dst,src);
	break;
    }
}


static void i_81pre(void)    /* Opcode 0x81 */
{
    unsigned ModRM = FETCH;
    unsigned dst = GetRMWord(ModRM);
    unsigned src = FETCH;
    src+= (FETCH << 8);
    cycle_count-=2;

    switch (ModRM & 0x38)
    {
    case 0x00:  /* ADD ew,d16 */
        ADDW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x08:  /* OR ew,d16 */
        ORW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x10:  /* ADC ew,d16 */
        src+=CF;
        ADDW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x18:  /* SBB ew,d16 */
        src+=CF;
        SUBW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x20:  /* AND ew,d16 */
        ANDW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x28:  /* SUB ew,d16 */
        SUBW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x30:  /* XOR ew,d16 */
        XORW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x38:  /* CMP ew,d16 */
        SUBW(dst,src);
	break;
    }
}

static void i_83pre(void)    /* Opcode 0x83 */
{
    unsigned ModRM = FETCH;
    unsigned dst = GetRMWord(ModRM);
    unsigned src = (WORD)((INT16)((INT8)FETCH));
    cycle_count-=2;

    switch (ModRM & 0x38)
    {
    case 0x00:  /* ADD ew,d8 */
        ADDW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x08:  /* OR ew,d8 */
        ORW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x10:  /* ADC ew,d8 */
        src+=CF;
        ADDW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x18:  /* SBB ew,d8 */
        src+=CF;
        SUBW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x20:  /* AND ew,d8 */
        ANDW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x28:  /* SUB ew,d8 */
        SUBW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x30:  /* XOR ew,d8 */
        XORW(dst,src);
        PutbackRMWord(ModRM,dst);
	break;
    case 0x38:  /* CMP ew,d8 */
        SUBW(dst,src);
	break;
    }
}

static void i_test_br8(void)    /* Opcode 0x84 */
{
    DEF_br8(dst,src);
    cycle_count-=3;
    ANDB(dst,src);